Simulation Results: clkmgr

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.88 %
  • code
  • 98.57 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.07 %
  • branch
  • 98.74 %
  • cond
  • 95.85 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
77.24%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.430s 91.806us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.600s 160.255us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.350s 98.036us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.740s 428.897us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.060s 160.327us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.450s 309.168us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.350s 98.036us 5 5 100.00
clkmgr_csr_aliasing 2.060s 160.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.450s 116.429us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.390s 68.869us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 2.210s 283.302us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.300s 110.399us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.430s 91.806us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 16.570s 1884.391us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 15.500s 1820.402us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 16.570s 1884.391us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 92.900s 13016.139us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 2.020s 260.149us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 7.030s 955.314us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 7.030s 955.314us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.600s 160.255us 1 1 100.00
clkmgr_csr_rw 1.350s 98.036us 5 5 100.00
clkmgr_csr_aliasing 2.060s 160.327us 1 1 100.00
clkmgr_same_csr_outstanding 2.520s 351.095us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.600s 160.255us 1 1 100.00
clkmgr_csr_rw 1.350s 98.036us 5 5 100.00
clkmgr_csr_aliasing 2.060s 160.327us 1 1 100.00
clkmgr_same_csr_outstanding 2.520s 351.095us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 16 30 53.33
clkmgr_sec_cm 29.160s 10015.355us 0 5 0.00
clkmgr_tl_intg_err 62.880s 10124.890us 16 25 64.00
shadow_reg_update_error 8 20 40.00
clkmgr_shadow_reg_errors 1058.840s 200000.000us 8 20 40.00
shadow_reg_read_clear_staged_value 8 20 40.00
clkmgr_shadow_reg_errors 1058.840s 200000.000us 8 20 40.00
shadow_reg_storage_error 8 20 40.00
clkmgr_shadow_reg_errors 1058.840s 200000.000us 8 20 40.00
shadowed_reset_glitch 8 20 40.00
clkmgr_shadow_reg_errors 1058.840s 200000.000us 8 20 40.00
shadow_reg_update_error_with_csr_rw 13 20 65.00
clkmgr_shadow_reg_errors_with_csr_rw 911.190s 200000.000us 13 20 65.00
sec_cm_bus_integrity 16 25 64.00
clkmgr_tl_intg_err 62.880s 10124.890us 16 25 64.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 16.570s 1884.391us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 15.500s 1820.402us 10 10 100.00
sec_cm_meas_config_shadow 8 20 40.00
clkmgr_shadow_reg_errors 1058.840s 200000.000us 8 20 40.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.470s 87.578us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.360s 60.094us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.550s 143.302us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_clk_handshake_intersig_mubi 2.200s 323.508us 10 10 100.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.960s 220.479us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.350s 98.036us 5 5 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 29.160s 10015.355us 0 5 0.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.350s 98.036us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.350s 98.036us 5 5 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 29.160s 10015.355us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 8.780s 1298.178us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 88.570s 6347.567us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 14 test runs
clkmgr_shadow_reg_errors 44834863678063884078073557142461749138355875854091672798949737557761269017914 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 33904010154026914160332350484257291126724423666928390121216217232104724712606 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 25160285727333331929321697147983198370874410064230283564807729059409148780256 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 4317297996189265795510721984919999202659969278419281538008114266414047060311 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 76810594001496046248858542341244864723850090704027845261331646401013329962225 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 62286091172099567534025721010765704471073350844792497882579572284170788953769 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 69989649122198811807245818488394528028508101903455500769413353026192600209874 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 94257153695747952814190624362340250134550914186995104929365343595049747883159 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 108441457759893398924587736526761301499677552088647684180860533868238987526683 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 96410192412972776463120785239086653080837922424090269184913583521992501952229 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 101079939779810962608533626951637782975638480195903755614231638000918714420819 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 14216306822831816509180100779029082923589524193982246898696721451827586434760 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 109968817679094200624416310491615615034667682817862868022814777423089214085626 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 32291820993761337078870541131397007256226116146532981837487132039657548944463 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 10 test runs
clkmgr_sec_cm 78837152595322108111145888749634930398676330123158653189899171673201858168331 80
UVM_INFO @ 10015355113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 53273722467964202585613231438167771208164344170866863351772144513099798458564 97
UVM_INFO @ 10023258644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 31789557162517344386878500912027790553902701429213945009793139550164318301439 90
UVM_INFO @ 10013484892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 92652826253284034204954158776347634541925630660161503027352953744444101815135 116
UVM_INFO @ 10054124747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 52496183057095850492888987282150316102076619573037675335443801858619896966566 97
UVM_INFO @ 10192631521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 62163143542668202043820940602775723768930157705665003174885737522344850657482 131
UVM_INFO @ 10117107096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 16025923704974096985443156682584045577074719639724244002202724768550779020361 226
UVM_INFO @ 10124889603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 82570285367667611316486338241546455994755887267889164621141417818609936301903 236
UVM_INFO @ 10108713651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 71609395054812345363504273725353481200054348186177892091746970854574551672797 102
UVM_INFO @ 10076711376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 6142754442968000500253375858680123924551407760994688213155316514215753194590 235
UVM_INFO @ 10117373021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 4 test runs
clkmgr_sec_cm 110276164097405928635755801062907328056353991928863337164305133275658335154815 126
UVM_INFO @ 112545759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 99924741435242029418067357314949571064387499730673314498019491245428667262920 78
UVM_INFO @ 2438436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 50159882325941380904151602633586392673678475907545075043662378631017667978840 85
UVM_INFO @ 11667336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 85883698922587408188817556668428697882883360260410079875617474403036810296660 77
UVM_INFO @ 2885113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_enable (addr=*) 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 19683442001525160646543842516470176207311113221722693217238289015149837362966 76
UVM_INFO @ 2079183801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 114081507406641521721071845409017997399231067417053584369156518905348928638664 75
UVM_INFO @ 2103218756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 30258711270990641187706950808499962729449187386465977114979978058716666293833 76
UVM_INFO @ 2114927926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 14970407395015210333531278857704033989048544195974734825206065169584463442811 75
UVM_INFO @ 2093972186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 57085593037334409697833933793857082812265075579137942753943595009575213293872 76
UVM_INFO @ 88960333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---