Simulation Results

Simulation Results: csrng

25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.73 %

code
96.17 %

assert
97.16 %

func
90.86 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		97.78%
V2S		98.83%
V3		10.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	23.000s	28.811us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	35.000s	35.157us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	36.000s	114.754us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	39.000s	168.399us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	39.000s	401.013us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	34.000s	17.452us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	36.000s	114.754us	5	5	100.00
	csrng_csr_aliasing	39.000s	401.013us	1	1	100.00

1278/1307 passed

97.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	54.000s	5269.190us	500	500	100.00
err				500	500	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
cmds				1	25	4.00
	csrng_cmds	38.000s	135.189us	1	25	4.00
life cycle				1	25	4.00
	csrng_cmds	38.000s	135.189us	1	25	4.00
stress_all				20	25	80.00
	csrng_stress_all	1070.000s	59019.275us	20	25	80.00
intr_test				10	10	100.00
	csrng_intr_test	31.000s	21.216us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	35.000s	74.309us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	23.000s	596.980us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	23.000s	596.980us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	35.000s	35.157us	1	1	100.00
	csrng_csr_rw	36.000s	114.754us	5	5	100.00
	csrng_csr_aliasing	39.000s	401.013us	1	1	100.00
	csrng_same_csr_outstanding	28.000s	28.790us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	35.000s	35.157us	1	1	100.00
	csrng_csr_rw	36.000s	114.754us	5	5	100.00
	csrng_csr_aliasing	39.000s	401.013us	1	1	100.00
	csrng_same_csr_outstanding	28.000s	28.790us	5	5	100.00

V2S

1270/1285 passed

98.83 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
	csrng_tl_intg_err	20.000s	1743.682us	25	25	100.00
sec_cm_config_regwen				20	30	66.67
	csrng_regwen	31.000s	16.937us	15	25	60.00
	csrng_csr_rw	36.000s	114.754us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	54.000s	5269.190us	500	500	100.00
sec_cm_intersig_mubi				20	25	80.00
	csrng_stress_all	1070.000s	59019.275us	20	25	80.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	54.000s	5269.190us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
sec_cm_constants_lc_gated				20	25	80.00
	csrng_stress_all	1070.000s	59019.275us	20	25	80.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	54.000s	5269.190us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	20.000s	1743.682us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00
	csrng_sec_cm	26.000s	65.768us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	35.000s	92.495us	200	200	100.00
	csrng_err	34.000s	45.708us	500	500	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				22 test runs
	csrng_cmds	31974478335780013199218933287614958444113796828953143124251170470108734600803	100	UVM_INFO @ 135188696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22949330306087460302786450232107458455031792305993747047698670485998396781450	100	UVM_INFO @ 208763030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100034008260248133237310572050495549965367456864809732937248437754330651171853	100	UVM_INFO @ 61767819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	78670888278739259800051822336850755338217111825428031588839308345195775222530	100	UVM_INFO @ 76929948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31868839157321003335290981154611259641809708565001559614792155250850877422329	100	UVM_INFO @ 80305590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	101412302131690405135885933716843576916987828396508007693283790852904260386459	100	UVM_INFO @ 14069761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93328595763905020417940889563108050654912064169960798055083323821001534227741	100	UVM_INFO @ 1091345276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	17839509144825097745874106078127948002367240830055312295446766910982170787021	100	UVM_INFO @ 123345761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	73403419716126624003198540400743082705300016226300213302217275651232516847691	100	UVM_INFO @ 134250643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15642946676067039804772609635801017773525474447083036441301217490145414581027	100	UVM_INFO @ 22566643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	36802945295895460375822208802930672227959535125150900248518198208856638202071	100	UVM_INFO @ 6026213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	66485427075937395316671771790670110088150243667831763415255468820557585574036	100	UVM_INFO @ 21300038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	14135220244733457354212810452076878316644816791468863270842443274916351165259	100	UVM_INFO @ 88271409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	87553705529954248239099395388294098832738715247585764212008151320424221994017	100	UVM_INFO @ 39730617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48155206478374804921050390139960150586125724997279987379097680214339474511779	100	UVM_INFO @ 222016077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	77201077972685057771146243457594653813237876915963215897253835407833131224975	100	UVM_INFO @ 396908937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	80088720553734235752190846767435193658543677405336274966540700641391459310858	100	UVM_INFO @ 85899696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83414194335739514444645366777758089801166274868564232539047509668257961480676	100	UVM_INFO @ 853090011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88426846906257421837482578675386068966905786491771824503211080977306016417984	100	UVM_INFO @ 36892316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	91963279087859187845174606380931755562861333989396071926532465961828021996926	100	UVM_INFO @ 512688214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68826877136133205684097960954252164957617305134282226097446042459364844018379	100	UVM_INFO @ 27466114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	85252526882380335766174548877036189960120924640638341691140398719708806413854	110	UVM_INFO @ 104816658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				9 test runs
	csrng_regwen	33029995413402350986918093477660258629979651542079807995913837950932329353535	99	UVM_INFO @ 12838621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	15919320673363830946362064453189199722017285847809333085598673324771078119489	99	UVM_INFO @ 1949237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	39102977891984877051035237719178231105421833458106420216285833518701832850931	99	UVM_INFO @ 5936173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	12061558634463074156250776202718619120803838094662372166259651018077360657872	99	UVM_INFO @ 11167463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	106382148466112553134634696133584317665554993969512568626016634281826038808615	99	UVM_INFO @ 4743044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	47626620418708886904984132668751145282065716885184109228885832232998679228844	99	UVM_INFO @ 8982784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	57934904017483975197970978768817521491093265082723747661472029694724764127159	99	UVM_INFO @ 12843319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	114707618496476871064482676908615892249521680360065082295279027113904932189964	99	UVM_INFO @ 1877502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	30179105395261220541244209599671579540437334522218586647345092780483290063293	99	UVM_INFO @ 1338081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				6 test runs
	csrng_stress_all_with_rand_reset	86164384154314161044857408331614739921420079756812662429681691722823878224016	119	UVM_INFO @ 303467136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	110132110668144417123573975704530688736512196739311191486396081026946697996722	106	UVM_INFO @ 88575969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	101501936413306743937719337670948614716901595352147223611481894609294919528453	110	UVM_INFO @ 3277969691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	32924897792247549919034608626554232954851420822540668412580728933116647613789	107	UVM_INFO @ 14019055071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	53714449894085280681456815867425081590074886639072707478371543834321354861951	114	UVM_INFO @ 23118793361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	66129986222755334579107378207340984395956906458627055853638597716031319989216	110	UVM_INFO @ 1303049999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				5 test runs
	csrng_stress_all_with_rand_reset	44724372456266258946761441949402601743155576452882831047866586191851731665269	None
	csrng_stress_all_with_rand_reset	62412259371579954960809472765294577632282625948509296170597282925635569590454	None
	csrng_stress_all_with_rand_reset	37707154221333647009852129185277903371514950441300058390358245357385936783463	None
	csrng_stress_all_with_rand_reset	14023472154471681368946779351103287484007518106362754413850976766669341375180	None
	csrng_stress_all_with_rand_reset	108148221853813857837950117765587968495258654276223875800408930670384903076800	None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				3 test runs
	csrng_stress_all_with_rand_reset	81181915244842322888192672875735386218250363691199392899649640046052329047208	157	UVM_INFO @ 767083042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	6150656472443892653837867593357485793127413880871191989358560460574404428555	107	UVM_INFO @ 1450396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	34617929369790611296019564520918032513530177557681673010110256657590652037305	110	UVM_INFO @ 33347982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				2 test runs
	csrng_cmds	41504937266914480678145335660532176264317532005975143368776953277722075513860	103	UVM_INFO @ 41779289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	9869970658821859373646610909761307635169107205463960747018328794212978713473	103	UVM_INFO @ 168257297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				1 test run
	csrng_regwen	25856922369120190080462254248099639250259141009955096488687814132476281338790	99	UVM_INFO @ 11938770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---