Simulation Results: edn/edn0

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.84 %
  • code
  • 95.95 %
  • assert
  • 98.92 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 93.01 %
Validation stages
V1
100.00%
V2
98.85%
V2S
100.00%
V3
96.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.320s 19.045us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.020s 15.766us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.250s 13.756us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.110s 340.669us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.020s 71.710us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.740s 129.269us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.250s 13.756us 5 5 100.00
edn_csr_aliasing 2.020s 71.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.500s 773.227us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.500s 773.227us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.500s 773.227us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.380s 24.220us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.680s 33.078us 200 200 100.00
errs 100 100 100.00
edn_err 1.690s 58.946us 100 100 100.00
disable 93 100 93.00
edn_disable 1.330s 14.041us 50 50 100.00
edn_disable_auto_req_mode 4.400s 500.000us 43 50 86.00
stress_all 30 30 100.00
edn_stress_all 7.390s 1216.561us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.240s 17.516us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.630s 31.056us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.550s 274.744us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.550s 274.744us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.020s 15.766us 1 1 100.00
edn_csr_rw 1.250s 13.756us 5 5 100.00
edn_csr_aliasing 2.020s 71.710us 1 1 100.00
edn_same_csr_outstanding 1.230s 162.893us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.020s 15.766us 1 1 100.00
edn_csr_rw 1.250s 13.756us 5 5 100.00
edn_csr_aliasing 2.020s 71.710us 1 1 100.00
edn_same_csr_outstanding 1.230s 162.893us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 9.570s 853.248us 5 5 100.00
edn_tl_intg_err 17.600s 1648.187us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.270s 37.203us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.680s 33.078us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.570s 853.248us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.570s 853.248us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.570s 853.248us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.570s 853.248us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.680s 33.078us 200 200 100.00
edn_sec_cm 9.570s 853.248us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.680s 33.078us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 17.600s 1648.187us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 30 96.67
edn_stress_all_with_rand_reset 76.700s 18939.303us 29 30 96.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 84667715899977819570894530733131991597963806955395144046344490860884194294516 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 73525681155696947234926607618533205798950892718251168244429289188625127970170 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88262045790517702411690568798267909577158144602698162229781343521330051922655 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 14842891500573869680135959921734932425111438181258127188283655640371712505994 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 79551195879443432912162471311533557352849123369411414039702964745340864079418 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 54775678598934222821459511036219076586062877683727017560151129592779774319173 88
UVM_INFO @ 36632505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 60156151120432224444713136135611282523896920070756717244262731598845488087752 88
UVM_INFO @ 175819312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 76850941029229309645711711959157008824085186387557866280937474348139828067965 354
UVM_INFO @ 3390216425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---