Simulation Results: edn/edn1

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.68 %
  • code
  • 95.90 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.85 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
98.68%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.000s 24.337us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 18.896us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.150s 35.343us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.570s 586.407us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.410s 377.544us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.340s 36.230us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.150s 35.343us 5 5 100.00
edn_csr_aliasing 1.410s 377.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 2.640s 231.747us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 2.640s 231.747us 100 100 100.00
genbits 100 100 100.00
edn_genbits 2.640s 231.747us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.090s 29.290us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.550s 96.491us 200 200 100.00
errs 100 100 100.00
edn_err 1.290s 70.849us 100 100 100.00
disable 92 100 92.00
edn_disable 1.180s 14.615us 50 50 100.00
edn_disable_auto_req_mode 11.750s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 6.170s 1665.452us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.070s 117.806us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.260s 20.038us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.330s 386.939us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.330s 386.939us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.860s 18.896us 1 1 100.00
edn_csr_rw 1.150s 35.343us 5 5 100.00
edn_csr_aliasing 1.410s 377.544us 1 1 100.00
edn_same_csr_outstanding 1.430s 27.532us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.860s 18.896us 1 1 100.00
edn_csr_rw 1.150s 35.343us 5 5 100.00
edn_csr_aliasing 1.410s 377.544us 1 1 100.00
edn_same_csr_outstanding 1.430s 27.532us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.280s 777.632us 5 5 100.00
edn_tl_intg_err 2.380s 205.289us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.200s 30.880us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.550s 96.491us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.280s 777.632us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.280s 777.632us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.280s 777.632us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.280s 777.632us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.550s 96.491us 200 200 100.00
edn_sec_cm 4.280s 777.632us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.550s 96.491us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.380s 205.289us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 103.620s 18057.760us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 7 test runs
edn_disable_auto_req_mode 3344570358311374195170555402497312130761713311218079618896953939315236064781 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 34691748881631039742758998853491180562187618352933209608901589899376215029044 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 114485762353766552906543250570315167772391676993598138271770934544540438728419 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 23602252061398541807670275536709440447536803777367952862646953612237628665704 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 60475693305269934746429433642260905220894269960491142710371338093919573539078 90
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 45617865812026000277634544628841217443508348502567915418166163580568467758993 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 49659635117985635511761227499465294130159964348975565820626244611380965687433 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 105285561365251900582649716392236879045307781886979205627397687813414127974618 216
UVM_INFO @ 1482116296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 58137849610603676447325180034211653571278659180512258839094524960843200196508 231
UVM_INFO @ 1051295216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 84247257981572396021455856001085176354159513841365526861910254006969454995627 168
UVM_INFO @ 1398012574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 100686723021332339486058249360475014154518898229489496914095396121471915664639 123
UVM_INFO @ 270994774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 37842907906888250000113842055542350749563240344242070402264781310563431441632 157
UVM_INFO @ 307216513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 55391022517591051696871678052206719524746573658635781142412649504331639698978 88
UVM_INFO @ 14048561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---