Simulation Results

Simulation Results: flash_ctrl

25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.89 %

code
95.36 %

assert
96.94 %

func
98.36 %

line
96.10 %

branch
97.42 %

cond
94.86 %

toggle
96.60 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		98.61%
V2S		99.16%
V3		100.00%
unmapped		100.00%

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	171.260s	4005.768us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	25.130s	62.072us	5	5	100.00
csr_hw_reset				1	1	100.00
	flash_ctrl_csr_hw_reset	33.180s	48.496us	1	1	100.00
csr_rw				5	5	100.00
	flash_ctrl_csr_rw	18.110s	267.661us	5	5	100.00
csr_bit_bash				1	1	100.00
	flash_ctrl_csr_bit_bash	43.480s	1815.082us	1	1	100.00
csr_aliasing				1	1	100.00
	flash_ctrl_csr_aliasing	25.920s	283.207us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	21.070s	125.139us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	flash_ctrl_csr_rw	18.110s	267.661us	5	5	100.00
	flash_ctrl_csr_aliasing	25.920s	283.207us	1	1	100.00
mem_walk				1	1	100.00
	flash_ctrl_mem_walk	9.570s	22.504us	1	1	100.00
mem_partial_access				1	1	100.00
	flash_ctrl_mem_partial_access	11.410s	19.718us	1	1	100.00

922/935 passed

98.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	25.460s	29.151us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	70.210s	126.858us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1433.200s	577779.269us	3	3	100.00
	flash_ctrl_hw_rma_reset	1056.610s	540457.175us	20	20	100.00
	flash_ctrl_lcmgr_intg	14.820s	22.226us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1813.380s	379697.441us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	408.240s	66674.658us	5	5	100.00
program_reset				29	30	96.67
	flash_ctrl_prog_reset	3604.012s	0.000us	29	30	96.67
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3164.870s	301260.479us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	105.690s	4243.420us	5	5	100.00
rd_buff_eviction_w_ecc				102	105	97.14
	flash_ctrl_rw_evict	33.300s	98.806us	38	40	95.00
	flash_ctrl_rw_evict_all_en	34.480s	42.511us	39	40	97.50
	flash_ctrl_re_evict	36.840s	80.692us	25	25	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	236.070s	1629.251us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	236.070s	1629.251us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	627.020s	13715.622us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	28.330s	1562.393us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	774.490s	477.139us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	697.090s	8487.999us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	599.730s	4496.559us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1184.640s	3632.855us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.190s	80.939us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	139.560s	2888.007us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	24.310s	103.697us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	18.550s	16.826us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	911.400s	519.449us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	178.180s	6914.063us	50	50	100.00
	flash_ctrl_otp_reset	126.720s	388.059us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1433.200s	577779.269us	3	3	100.00
interrupts				98	100	98.00
	flash_ctrl_intr_rd	198.130s	25227.325us	38	40	95.00
	flash_ctrl_intr_wr	102.610s	51997.613us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	367.300s	13614.483us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	206.280s	79945.149us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	65.510s	988.894us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	66.660s	1703.546us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	24.940s	116.993us	5	5	100.00
	flash_ctrl_ro_derr	122.200s	11029.161us	10	10	100.00
	flash_ctrl_rw_derr	178.900s	34954.780us	10	10	100.00
	flash_ctrl_derr_detect	144.240s	780.128us	5	5	100.00
	flash_ctrl_integrity	446.610s	18182.506us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	20.290s	30.867us	5	5	100.00
	flash_ctrl_ro_serr	113.160s	2410.603us	10	10	100.00
	flash_ctrl_rw_serr	182.940s	4584.292us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	76.540s	945.222us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	63.570s	1488.270us	5	5	100.00
scramble				55	62	88.71
	flash_ctrl_wo	3604.014s	0.000us	18	20	90.00
	flash_ctrl_write_word_sweep	14.320s	82.429us	1	1	100.00
	flash_ctrl_read_word_sweep	13.510s	198.954us	1	1	100.00
	flash_ctrl_ro	117.200s	12411.269us	19	20	95.00
	flash_ctrl_rw	3604.011s	0.000us	16	20	80.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	32.930s	1680.945us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	776.470s	157792.345us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	235.360s	10020.121us	20	20	100.00
alert_test				10	10	100.00
	flash_ctrl_alert_test	13.200s	164.165us	10	10	100.00
intr_test				10	10	100.00
	flash_ctrl_intr_test	15.040s	54.837us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	flash_ctrl_tl_errors	19.010s	408.745us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	flash_ctrl_tl_errors	19.010s	408.745us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	flash_ctrl_csr_hw_reset	33.180s	48.496us	1	1	100.00
	flash_ctrl_csr_rw	18.110s	267.661us	5	5	100.00
	flash_ctrl_csr_aliasing	25.920s	283.207us	1	1	100.00
	flash_ctrl_same_csr_outstanding	23.300s	195.071us	5	5	100.00
tl_d_partial_access				12	12	100.00
	flash_ctrl_csr_hw_reset	33.180s	48.496us	1	1	100.00
	flash_ctrl_csr_rw	18.110s	267.661us	5	5	100.00
	flash_ctrl_csr_aliasing	25.920s	283.207us	1	1	100.00
	flash_ctrl_same_csr_outstanding	23.300s	195.071us	5	5	100.00

V2S

471/475 passed

99.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	79.220s	102.080us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	79.220s	102.080us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	79.220s	102.080us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	79.220s	102.080us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	83.350s	2202.361us	20	20	100.00
tl_intg_err				30	30	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00
	flash_ctrl_tl_intg_err	637.790s	3104.706us	25	25	100.00
sec_cm_reg_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	637.790s	3104.706us	25	25	100.00
sec_cm_host_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	637.790s	3104.706us	25	25	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	34.360s	84.242us	3	3	100.00
	flash_ctrl_wr_intg	11.850s	48.858us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	171.260s	4005.768us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	126.720s	388.059us	80	80	100.00
	flash_ctrl_disable	24.310s	103.697us	50	50	100.00
	flash_ctrl_sec_info_access	89.520s	5542.057us	50	50	100.00
	flash_ctrl_connect	18.550s	16.826us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	14.620s	125.675us	5	5	100.00
sec_cm_data_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	18.110s	267.661us	5	5	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	79.220s	102.080us	20	20	100.00
sec_cm_info_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	18.110s	267.661us	5	5	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	79.220s	102.080us	20	20	100.00
sec_cm_bank_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	18.110s	267.661us	5	5	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	79.220s	102.080us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	24.310s	103.697us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	34.360s	84.242us	3	3	100.00
	flash_ctrl_access_after_disable	12.420s	49.157us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	25.370s	41.545us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	24.310s	103.697us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	28.330s	1562.393us	10	10	100.00
sec_cm_mem_scramble				16	20	80.00
	flash_ctrl_rw	3604.011s	0.000us	16	20	80.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	182.940s	4584.292us	10	10	100.00
	flash_ctrl_rw_derr	178.900s	34954.780us	10	10	100.00
	flash_ctrl_integrity	446.610s	18182.506us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1433.200s	577779.269us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	20.160s	683.989us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_host_grant_err	13.940s	168.775us	5	5	100.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	15.380s	121.148us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2541.700s	5696.895us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	45.170s	107.695us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	382.510s	2600.712us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				6 test runs
	flash_ctrl_prog_reset	98261443504105755308069353068738179773213978021392961473524662510436222314738	None
	flash_ctrl_rw	67012470772547685584770302544008400364660267757854804651284697650265986601476	None
	flash_ctrl_rw	56419319167278507410128816020465245228771261838253153745831961027189966771894	None
	flash_ctrl_wo	33789350268465600571107931939273895585517757480049077336416124178842641250119	None
	flash_ctrl_wo	65712132897333758179072482977347917608321199121788449607819022997371989389612	None
	flash_ctrl_rw	73010554315493574288411721762048474390246432109182686233941584480121216809690	None
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_err triggered unexpectedly				2 test runs
	flash_ctrl_ro	51011971291563139026959040662689191583309514207366638682131617214664949389541	108	UVM_INFO @ 664079.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw	90852435188770939404429467636975514643178723326355526206175254666360249776891	108	UVM_INFO @ 7500470.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				2 test runs
	flash_ctrl_rw_evict_all_en	39217257510340501294592403078855095464501043386627026555661295645094068029220	108	UVM_INFO @ 10608.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	76621364712833936207097534897222493482864054922509675726373052919190285074233	108	UVM_INFO @ 70210.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:				1 test run
	flash_ctrl_rw_evict	88428798380505424492370542477896645709670603981818651164748170301189263338647	108	UVM_INFO @ 18172.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp ba0a4628_529bf9f5:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	31619457374516016652386477810640259569694000507784310094789242338237245107249	108	UVM_INFO @ 3992713.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp b9e6e22_96d70db8:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	43282270880739446662397286335286275262987377719891403472557605754619882909530	108	UVM_INFO @ 2481779.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---