Simulation Results: hmac

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.39 %
  • code
  • 99.20 %
  • assert
  • 96.29 %
  • func
  • 99.68 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.100s 437.582us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.080s 31.887us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.200s 109.420us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.030s 581.590us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.110s 240.656us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 2.230s 22.070us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.200s 109.420us 5 5 100.00
hmac_csr_aliasing 2.110s 240.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 84.330s 33903.703us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 107.370s 23635.080us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 256.000s 11967.340us 30 30 100.00
hmac_test_sha384_vectors 565.460s 113863.836us 75 75 100.00
hmac_test_sha512_vectors 557.770s 44668.881us 75 75 100.00
hmac_test_hmac256_vectors 15.960s 7771.534us 50 50 100.00
hmac_test_hmac384_vectors 19.410s 1962.031us 60 60 100.00
hmac_test_hmac512_vectors 19.020s 8268.294us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 41.130s 3063.917us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1598.190s 24581.323us 10 10 100.00
error 10 10 100.00
hmac_error 94.670s 73727.735us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 108.360s 6121.476us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.100s 437.582us 10 10 100.00
hmac_long_msg 84.330s 33903.703us 10 10 100.00
hmac_back_pressure 107.370s 23635.080us 25 25 100.00
hmac_datapath_stress 1598.190s 24581.323us 10 10 100.00
hmac_burst_wr 41.130s 3063.917us 50 50 100.00
hmac_stress_all 2607.690s 249684.687us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.100s 437.582us 10 10 100.00
hmac_long_msg 84.330s 33903.703us 10 10 100.00
hmac_back_pressure 107.370s 23635.080us 25 25 100.00
hmac_datapath_stress 1598.190s 24581.323us 10 10 100.00
hmac_wipe_secret 108.360s 6121.476us 10 10 100.00
hmac_test_sha256_vectors 256.000s 11967.340us 30 30 100.00
hmac_test_sha384_vectors 565.460s 113863.836us 75 75 100.00
hmac_test_sha512_vectors 557.770s 44668.881us 75 75 100.00
hmac_test_hmac256_vectors 15.960s 7771.534us 50 50 100.00
hmac_test_hmac384_vectors 19.410s 1962.031us 60 60 100.00
hmac_test_hmac512_vectors 19.020s 8268.294us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.100s 437.582us 10 10 100.00
hmac_long_msg 84.330s 33903.703us 10 10 100.00
hmac_back_pressure 107.370s 23635.080us 25 25 100.00
hmac_datapath_stress 1598.190s 24581.323us 10 10 100.00
hmac_burst_wr 41.130s 3063.917us 50 50 100.00
hmac_error 94.670s 73727.735us 10 10 100.00
hmac_wipe_secret 108.360s 6121.476us 10 10 100.00
hmac_test_sha256_vectors 256.000s 11967.340us 30 30 100.00
hmac_test_sha384_vectors 565.460s 113863.836us 75 75 100.00
hmac_test_sha512_vectors 557.770s 44668.881us 75 75 100.00
hmac_test_hmac256_vectors 15.960s 7771.534us 50 50 100.00
hmac_test_hmac384_vectors 19.410s 1962.031us 60 60 100.00
hmac_test_hmac512_vectors 19.020s 8268.294us 75 75 100.00
hmac_stress_all 2607.690s 249684.687us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2607.690s 249684.687us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.920s 21.168us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.970s 67.995us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.400s 1264.889us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.400s 1264.889us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.080s 31.887us 1 1 100.00
hmac_csr_rw 1.200s 109.420us 5 5 100.00
hmac_csr_aliasing 2.110s 240.656us 1 1 100.00
hmac_same_csr_outstanding 1.930s 70.256us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.080s 31.887us 1 1 100.00
hmac_csr_rw 1.200s 109.420us 5 5 100.00
hmac_csr_aliasing 2.110s 240.656us 1 1 100.00
hmac_same_csr_outstanding 1.930s 70.256us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.380s 110.133us 5 5 100.00
hmac_tl_intg_err 5.130s 264.658us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.130s 264.658us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.100s 437.582us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.680s 917.011us 25 25 100.00
stress_all_with_rand_reset 34 35 97.14
hmac_stress_all_with_rand_reset 594.580s 72050.501us 34 35 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.720s 156.791us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [hmac_common_vseq] wait timeout occurred! 1 test run
hmac_stress_all_with_rand_reset 179402163681517109780521882728078775426565560019667084398044761286126194311 145
UVM_INFO @ 10073027618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---