Simulation Results: keymgr

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.71 %
  • code
  • 98.36 %
  • assert
  • 97.72 %
  • func
  • 91.05 %
  • line
  • 99.16 %
  • branch
  • 99.09 %
  • cond
  • 98.20 %
  • toggle
  • 97.68 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.06%
V2S
99.08%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 2.750s 351.683us 30 30 100.00
random 30 30 100.00
keymgr_random 5.110s 1353.952us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.340s 31.522us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.580s 171.750us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.680s 785.841us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 7.140s 255.726us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.820s 97.241us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.580s 171.750us 5 5 100.00
keymgr_csr_aliasing 7.140s 255.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 4.190s 73.759us 49 50 98.00
sideload 80 80 100.00
keymgr_sideload 3.780s 1989.327us 20 20 100.00
keymgr_sideload_kmac 3.530s 401.974us 20 20 100.00
keymgr_sideload_aes 2.980s 145.237us 20 20 100.00
keymgr_sideload_otbn 3.450s 341.073us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 3.590s 111.044us 30 30 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 4.990s 770.696us 48 50 96.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 4.480s 147.048us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 5.760s 2676.895us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 4.840s 1017.095us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 3.280s 221.411us 20 20 100.00
stress_all 49 50 98.00
keymgr_stress_all 43.890s 6818.015us 49 50 98.00
intr_test 10 10 100.00
keymgr_intr_test 1.090s 11.895us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.100s 20.741us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 3.910s 664.202us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 3.910s 664.202us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.340s 31.522us 1 1 100.00
keymgr_csr_rw 1.580s 171.750us 5 5 100.00
keymgr_csr_aliasing 7.140s 255.726us 1 1 100.00
keymgr_same_csr_outstanding 2.060s 128.818us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.340s 31.522us 1 1 100.00
keymgr_csr_rw 1.580s 171.750us 5 5 100.00
keymgr_csr_aliasing 7.140s 255.726us 1 1 100.00
keymgr_same_csr_outstanding 2.060s 128.818us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
keymgr_tl_intg_err 7.600s 1097.246us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 3.900s 1060.548us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 3.900s 1060.548us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 3.900s 1060.548us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 3.900s 1060.548us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 11.910s 476.907us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 7.600s 1097.246us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 3.900s 1060.548us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 4.190s 73.759us 49 50 98.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 5.110s 1353.952us 30 30 100.00
keymgr_csr_rw 1.580s 171.750us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 5.110s 1353.952us 30 30 100.00
keymgr_csr_rw 1.580s 171.750us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 5.110s 1353.952us 30 30 100.00
keymgr_csr_rw 1.580s 171.750us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 4.990s 770.696us 48 50 96.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 4.840s 1017.095us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 4.840s 1017.095us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 5.110s 1353.952us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 2.840s 149.758us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 5.500s 582.243us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 4.990s 770.696us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 5.500s 582.243us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 5.500s 582.243us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 5.500s 582.243us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.020s 1028.418us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 5.500s 582.243us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
keymgr_stress_all_with_rand_reset 27.900s 10152.129us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
keymgr_stress_all_with_rand_reset 51180233096266702226328946885836302715294387959382828195329152328090824276575 579
UVM_INFO @ 495786695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 75355837876863853102376171927143749946266351009857005652679387795724296478546 821
UVM_INFO @ 1001695404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:806) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start 1 test run
keymgr_cfg_regwen 67828743329730245484276180116574802217841125294492786633884263206100447267642 103
UVM_INFO @ 88167980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [keymgr_common_vseq] wait timeout occurred! 1 test run
keymgr_stress_all_with_rand_reset 51907273841884790223761059907697672399683476419396975578642502121323058355286 444
UVM_INFO @ 10152129500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:778) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_lc_disable 80070244445991338769255649499330348649268150781217783511964851902827385246685 276
UVM_INFO @ 441834622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:778) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 1 test run
keymgr_stress_all 19441583746424472586452160776661129510113369319541683294777286295600686588929 2457
UVM_INFO @ 1059697928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:547) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes 1 test run
keymgr_lc_disable 92213845731853621445127539689529542514198727280703565627199849598816953187480 305
UVM_INFO @ 164589433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---