Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.21 %
  • code
  • 85.69 %
  • assert
  • 94.69 %
  • func
  • 96.24 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 81.70 %
  • toggle
  • 88.33 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
99.30%
V2S
100.00%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 2.610s 218.688us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.360s 22.073us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.260s 67.709us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.300s 547.709us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 88.563us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.030s 61.703us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.260s 67.709us 5 5 100.00
lc_ctrl_csr_aliasing 1.480s 88.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.750s 161.444us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.620s 1731.757us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.180s 13.764us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.720s 133.688us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 10.620s 601.528us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_prog_failure 3.720s 133.688us 20 20 100.00
lc_ctrl_errors 10.620s 601.528us 20 20 100.00
lc_ctrl_security_escalation 9.450s 418.907us 20 20 100.00
lc_ctrl_jtag_state_failure 50.210s 22068.125us 20 20 100.00
lc_ctrl_jtag_prog_failure 10.380s 536.294us 20 20 100.00
lc_ctrl_jtag_errors 52.220s 61558.070us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 11.160s 3068.247us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.020s 1895.640us 20 20 100.00
lc_ctrl_jtag_prog_failure 10.380s 536.294us 20 20 100.00
lc_ctrl_jtag_errors 52.220s 61558.070us 19 20 95.00
lc_ctrl_jtag_access 15.970s 5028.602us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 17.340s 2353.918us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.990s 197.398us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.080s 184.607us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 19.910s 2513.686us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 7.190s 2705.961us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.920s 183.444us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.990s 1398.699us 10 10 100.00
lc_ctrl_jtag_alert_test 1.750s 51.960us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 9.730s 596.263us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.300s 23.671us 10 10 100.00
stress_all 8 10 80.00
lc_ctrl_stress_all 193.040s 13167.363us 8 10 80.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.320s 21.505us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.050s 142.069us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.050s 142.069us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.360s 22.073us 1 1 100.00
lc_ctrl_csr_rw 1.260s 67.709us 5 5 100.00
lc_ctrl_csr_aliasing 1.480s 88.563us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.600s 51.505us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.360s 22.073us 1 1 100.00
lc_ctrl_csr_rw 1.260s 67.709us 5 5 100.00
lc_ctrl_csr_aliasing 1.480s 88.563us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.600s 51.505us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
lc_ctrl_tl_intg_err 3.630s 642.008us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.630s 642.008us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.620s 1731.757us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.230s 1423.093us 20 20 100.00
lc_ctrl_sec_cm 10.490s 259.901us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 9.450s 418.907us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.750s 161.444us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.020s 1895.640us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.890s 1044.330us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.890s 1044.330us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.810s 1939.879us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.050s 851.451us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.050s 851.451us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 61.310s 3708.474us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 80647051055401884866734555523205422031135848193919455865550162619846292945311 369
UVM_INFO @ 386603790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65334397708913437844001541059949621952220397030685190779755775424854536468232 3539
UVM_INFO @ 1183340396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73237427067916062816912204273402559217280037509186336319689442955465247084815 6707
UVM_INFO @ 3708474274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 78065854057775742976579776238437382713637349789464005460769910619682530723871 4869
UVM_INFO @ 1245287254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22248808754131722224611607517786440970752586054591647743419236877330174777853 2498
UVM_INFO @ 13410270088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46256053770440347528791524865013648164905294315395890597382680414476211704471 3739
UVM_INFO @ 3027823649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_stress_all 88748702160432807108135066569715431991211866802068105412528087182750974752392 11414
UVM_INFO @ 13167362520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 103221214425255103245994527850483482925065381621959017831685149392823737999912 770
UVM_INFO @ 463505089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 35815604859342503018575667800432225987200228707176879221813390336257349520494 4517
UVM_INFO @ 7410082074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:252) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* 1 test run
lc_ctrl_stress_all_with_rand_reset 69683460870229029058521764380531762963563149018256397644167592102950129395564 494
UVM_INFO @ 1142527096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---