Simulation Results: lc_ctrl/volatile_unlock_enabled

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.35 %
  • code
  • 86.15 %
  • assert
  • 94.83 %
  • func
  • 96.06 %
  • line
  • 97.26 %
  • branch
  • 94.09 %
  • cond
  • 81.89 %
  • toggle
  • 88.33 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 2.590s 44.249us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.220s 81.612us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.220s 15.702us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.510s 25.106us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.540s 54.827us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.740s 29.966us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.220s 15.702us 5 5 100.00
lc_ctrl_csr_aliasing 1.540s 54.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 7.120s 154.657us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.810s 389.556us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.190s 23.038us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.120s 495.346us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 8.890s 1116.707us 20 20 100.00
security_escalation 140 140 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_prog_failure 3.120s 495.346us 20 20 100.00
lc_ctrl_errors 8.890s 1116.707us 20 20 100.00
lc_ctrl_security_escalation 8.140s 1054.275us 20 20 100.00
lc_ctrl_jtag_state_failure 39.000s 3591.966us 20 20 100.00
lc_ctrl_jtag_prog_failure 9.750s 1671.588us 20 20 100.00
lc_ctrl_jtag_errors 36.440s 2824.385us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 8.230s 1580.668us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.010s 3497.074us 20 20 100.00
lc_ctrl_jtag_prog_failure 9.750s 1671.588us 20 20 100.00
lc_ctrl_jtag_errors 36.440s 2824.385us 20 20 100.00
lc_ctrl_jtag_access 9.290s 1870.124us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 18.490s 1214.406us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.330s 204.712us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.090s 97.448us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 10.850s 2390.086us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 10.360s 1184.098us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.580s 74.852us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.710s 469.048us 10 10 100.00
lc_ctrl_jtag_alert_test 2.260s 426.490us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 16.410s 3357.996us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.330s 28.675us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 147.370s 35130.571us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.240s 24.025us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.330s 151.716us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.330s 151.716us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.220s 81.612us 1 1 100.00
lc_ctrl_csr_rw 1.220s 15.702us 5 5 100.00
lc_ctrl_csr_aliasing 1.540s 54.827us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 32.388us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.220s 81.612us 1 1 100.00
lc_ctrl_csr_rw 1.220s 15.702us 5 5 100.00
lc_ctrl_csr_aliasing 1.540s 54.827us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 32.388us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
lc_ctrl_tl_intg_err 2.980s 147.716us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 2.980s 147.716us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.810s 389.556us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 11.880s 789.768us 20 20 100.00
lc_ctrl_sec_cm 9.200s 511.752us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 8.140s 1054.275us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 7.120s 154.657us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.010s 3497.074us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.560s 430.105us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.560s 430.105us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.050s 1860.338us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.740s 951.975us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.740s 951.975us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 48.840s 4261.187us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
lc_ctrl_stress_all_with_rand_reset 33647555037463233686483989693885695178836543222630019646939548252150912412773 1005
UVM_INFO @ 3113674843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53115272286695872235910007983357391022275999570697983590143597684765026107574 7487
UVM_INFO @ 2826158632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65376214164059342163462922792385330969919672015816000020988721986016598421626 1462
UVM_INFO @ 2338698398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:252) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStScrap 1 test run
lc_ctrl_stress_all_with_rand_reset 35271235387564125209959317218916019085671318080211401050001768100288832755092 3367
UVM_INFO @ 3871413359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---