Simulation Results

Simulation Results: otbn

25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.75 %

code
87.12 %

assert
97.14 %

func
100.00 %

block
99.37 %

line
99.56 %

branch
95.44 %

toggle
85.88 %

FSM
67.61 %

Validation stages

V1		100.00%
V2		99.39%
V2S		98.48%
V3		50.00%
unmapped		100.00%

116/116 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	42.000s	158.536us	1	1	100.00
single_binary				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	41.000s	17.252us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	41.000s	42.731us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	42.000s	29.097us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	41.000s	16.294us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	42.000s	40.326us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	41.000s	42.731us	5	5	100.00
	otbn_csr_aliasing	41.000s	16.294us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	149.000s	6451.218us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	71.000s	342.162us	1	1	100.00

162/163 passed

99.39 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	200.000s	759.894us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	92.000s	193.945us	1	1	100.00
back_to_back				10	10	100.00
	otbn_multi	190.000s	471.806us	10	10	100.00
stress_all				10	10	100.00
	otbn_stress_all	471.000s	1168.688us	10	10	100.00
lc_escalation				59	60	98.33
	otbn_escalate	45.000s	23.465us	59	60	98.33
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	12.000s	41.875us	5	5	100.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	28.000s	67.119us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	42.000s	45.218us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	41.000s	18.139us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	17.000s	33.132us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	17.000s	33.132us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	41.000s	17.252us	1	1	100.00
	otbn_csr_rw	41.000s	42.731us	5	5	100.00
	otbn_csr_aliasing	41.000s	16.294us	1	1	100.00
	otbn_same_csr_outstanding	38.000s	101.631us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	41.000s	17.252us	1	1	100.00
	otbn_csr_rw	41.000s	42.731us	5	5	100.00
	otbn_csr_aliasing	41.000s	16.294us	1	1	100.00
	otbn_same_csr_outstanding	38.000s	101.631us	5	5	100.00

V2S

324/329 passed

98.48 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				24	25	96.00
	otbn_imem_err	45.000s	18.596us	9	10	90.00
	otbn_dmem_err	45.000s	35.902us	15	15	100.00
internal_integrity				17	17	100.00
	otbn_alu_bignum_mod_err	44.000s	20.246us	5	5	100.00
	otbn_controller_ispr_rdata_err	44.000s	14.361us	5	5	100.00
	otbn_mac_bignum_acc_err	48.000s	30.380us	5	5	100.00
	otbn_urnd_err	11.000s	27.173us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	40.000s	48.381us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	42.000s	14.201us	2	2	100.00
otbn_non_sec_partial_wipe				9	10	90.00
	otbn_partial_wipe	41.000s	91.394us	9	10	90.00
tl_intg_err				30	30	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
	otbn_tl_intg_err	63.000s	376.500us	25	25	100.00
passthru_mem_tl_intg_err				5	5	100.00
	otbn_passthru_mem_tl_intg_err	76.000s	124.238us	5	5	100.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	42.000s	158.536us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	45.000s	35.902us	15	15	100.00
sec_cm_instruction_mem_integrity				9	10	90.00
	otbn_imem_err	45.000s	18.596us	9	10	90.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	63.000s	376.500us	25	25	100.00
sec_cm_controller_fsm_global_esc				59	60	98.33
	otbn_escalate	45.000s	23.465us	59	60	98.33
sec_cm_controller_fsm_local_esc				39	40	97.50
	otbn_imem_err	45.000s	18.596us	9	10	90.00
	otbn_dmem_err	45.000s	35.902us	15	15	100.00
	otbn_zero_state_err_urnd	12.000s	41.875us	5	5	100.00
	otbn_illegal_mem_acc	40.000s	48.381us	5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_scramble_key_sideload				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_scramble_ctrl_fsm_local_esc				39	40	97.50
	otbn_imem_err	45.000s	18.596us	9	10	90.00
	otbn_dmem_err	45.000s	35.902us	15	15	100.00
	otbn_zero_state_err_urnd	12.000s	41.875us	5	5	100.00
	otbn_illegal_mem_acc	40.000s	48.381us	5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				59	60	98.33
	otbn_escalate	45.000s	23.465us	59	60	98.33
sec_cm_start_stop_ctrl_fsm_local_esc				39	40	97.50
	otbn_imem_err	45.000s	18.596us	9	10	90.00
	otbn_dmem_err	45.000s	35.902us	15	15	100.00
	otbn_zero_state_err_urnd	12.000s	41.875us	5	5	100.00
	otbn_illegal_mem_acc	40.000s	48.381us	5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_data_reg_sw_sca				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_ctrl_redun				11	12	91.67
	otbn_ctrl_redun	42.000s	26.501us	11	12	91.67
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	43.000s	50.221us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	96.000s	1095.420us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	96.000s	1095.420us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	41.000s	19.499us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				10	10	100.00
	otbn_rf_bignum_intg_err	92.000s	321.449us	10	10	100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00
sec_cm_loop_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	26.000s	18.967us	4	5	80.00
sec_cm_call_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	26.000s	18.967us	4	5	80.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	36.000s	26.721us	7	7	100.00
sec_cm_data_mem_sec_wipe				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_instruction_mem_sec_wipe				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_data_reg_sw_sec_wipe				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_write_mem_integrity				10	10	100.00
	otbn_multi	190.000s	471.806us	10	10	100.00
sec_cm_ctrl_flow_count				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_ctrl_flow_sca				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	19.000s	38.279us	5	5	100.00
sec_cm_key_sideload				100	100	100.00
	otbn_single	95.000s	338.268us	100	100	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	490.000s	26129.588us	5	5	100.00

5/10 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				5	10	50.00
	otbn_stress_all_with_rand_reset	598.000s	1563.041us	5	10	50.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	35.000s	34.703us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				5 test runs
	otbn_stress_all_with_rand_reset	89700807521201899367908655078676912031720271435562629408220141073150975537040	187	UVM_INFO @ 992174306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	99864529654952496626303387642424836087748362608508780537876122470660225319992	281	UVM_INFO @ 2336880980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	93718080248413216334865821823765884296348178442174872994361050267960273709279	401	UVM_INFO @ 1784858677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	8469286509042778854824977034798109674464410543393625177308984891809418845315	168	UVM_INFO @ 826902150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	28926203963883211435230541672007606193247619659186400563438766915616208787249	647	UVM_INFO @ 1563041104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				3 test runs
	otbn_stack_addr_integ_chk	36872459890736542918432367602362410945423515398966892454658762778364288285550	110	UVM_ERROR @ 9191951 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 9191951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_ctrl_redun	44201609303747125947270500638410074682987494863909722689616221331330997089137	107	UVM_ERROR @ 8648839 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 8648839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	81503439479929210238312050100878273384691588689564289460940483629899887976221	116	UVM_ERROR @ 26595673 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 26595673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				1 test run
	otbn_imem_err	95797174627443317151584205793708955619166999354075523640109492327402466332485	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status				1 test run
	otbn_partial_wipe	27274763468881327199798475526954296549329221105254468715012204882180868177985	117	UVM_INFO @ 15214310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---