Simulation Results: otp_ctrl

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.18 %
  • code
  • 85.56 %
  • assert
  • 95.47 %
  • func
  • 92.52 %
  • line
  • 90.31 %
  • branch
  • 86.89 %
  • cond
  • 94.08 %
  • toggle
  • 92.64 %
  • FSM
  • 63.89 %
Validation stages
V1
100.00%
V2
95.35%
V2S
95.00%
V3
22.77%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.850s 820.910us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 13.850s 7980.386us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.950s 1473.494us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.110s 88.518us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 10.530s 1173.830us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.320s 1232.204us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.480s 1652.544us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.110s 88.518us 5 5 100.00
otp_ctrl_csr_aliasing 4.320s 1232.204us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.670s 79.575us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.050s 549.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.600s 1849.916us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 6.750s 3154.737us 300 300 100.00
partition_check 31 60 51.67
otp_ctrl_background_chks 24.950s 5850.645us 10 10 100.00
otp_ctrl_check_fail 29.280s 18879.025us 21 50 42.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 9.280s 466.892us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 32.630s 12478.428us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 28.990s 4431.373us 10 10 100.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 1025.440s 200000.000us 9 10 90.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
otp_dai_errors 24 25 96.00
otp_ctrl_dai_errs 32.190s 6299.106us 24 25 96.00
otp_macro_errors 6 10 60.00
otp_ctrl_macro_errs 30.670s 5300.146us 6 10 60.00
test_access 10 10 100.00
otp_ctrl_test_access 38.430s 4294.490us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 274.450s 119426.901us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.920s 49.889us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.330s 129.154us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 6.950s 2273.100us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 6.950s 2273.100us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.950s 1473.494us 1 1 100.00
otp_ctrl_csr_rw 2.110s 88.518us 5 5 100.00
otp_ctrl_csr_aliasing 4.320s 1232.204us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.950s 2119.725us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.950s 1473.494us 1 1 100.00
otp_ctrl_csr_rw 2.110s 88.518us 5 5 100.00
otp_ctrl_csr_aliasing 4.320s 1232.204us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.950s 2119.725us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
otp_ctrl_tl_intg_err 27.690s 19179.161us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 27.690s 19179.161us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 13.850s 7980.386us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 13.850s 7980.386us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
sec_cm_part_fsm_local_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
otp_ctrl_macro_errs 30.670s 5300.146us 6 10 60.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
sec_cm_part_fsm_global_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
otp_ctrl_macro_errs 30.670s 5300.146us 6 10 60.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 47.630s 22696.836us 200 200 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 6.750s 3154.737us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 21 50 42.00
otp_ctrl_check_fail 29.280s 18879.025us 21 50 42.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 32.630s 12478.428us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 32.630s 12478.428us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 32.630s 12478.428us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 32.630s 12478.428us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 32.630s 12478.428us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 13.850s 7980.386us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 32.630s 12478.428us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 13.850s 7980.386us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 136.100s 11340.473us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 9.280s 466.892us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 13.850s 7980.386us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 13.850s 7980.386us 10 10 100.00
sec_cm_macro_mem_integrity 6 10 60.00
otp_ctrl_macro_errs 30.670s 5300.146us 6 10 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.920s 8035.880us 1 1 100.00
stress_all_with_rand_reset 22 100 22.00
otp_ctrl_stress_all_with_rand_reset 167.650s 54557.898us 22 100 22.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 49 test runs
otp_ctrl_dai_errs 83593671495393804092743610900876550779123218191885854355993816419488552657039 1463
UVM_INFO @ 506555408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 36479974345135906564063108094940487502563348068495738594347593061474532593788 699
UVM_INFO @ 2509862105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 75510080010217907940559279405810748695414294514543959876138915617441913356917 321
UVM_INFO @ 334114080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 181720138771415380337455827989551691717089152010125613177723885709584139984 2083
UVM_INFO @ 1865735555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 58984308477244674047944197691026236957339209180963127787897723336427995842132 11288
UVM_INFO @ 1242201824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 14644210825977832613166406231638521262533057024395347468508305366643164749875 1371
UVM_INFO @ 820137346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69688000648184427393852348620202236281428215502424725522062942676254636572219 8519
UVM_INFO @ 1281457935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 80479524259728612477945413156887917703766326212935250518748333934369967730469 2083
UVM_INFO @ 409123030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 75744548332439198993852674770230751143608526431483755857349607526685140253259 4669
UVM_INFO @ 4721797779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 23871392345439788757139429916252190750136253254773522350333726361019095599817 6720
UVM_INFO @ 298737355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 98423735707153742789803053290002276330919544818945985805530582530291015772297 3482
UVM_INFO @ 2093886842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 2689623284983114139565063551996394326062089049844728943794357482468530084163 8193
UVM_INFO @ 3596433203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 59008396434281336672485752242692935374738634504853911281622717119182995539822 407
UVM_INFO @ 47925984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 47650410584012682007016166094094417597838624161993605858055431760288818536066 613
UVM_INFO @ 1036022179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54659047427072328252946860850971800959411481395260755232288127406564426774502 1547
UVM_INFO @ 325812393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 51412164412179157984667271238024715180461604481128335381630284005399084830625 1383
UVM_INFO @ 550976878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86806942106891014675620106785913074294655871964197916488494806273533668585742 4892
UVM_INFO @ 1679460558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 11230091055242027979753538124117240015520451017746853094793886324944195610582 4267
UVM_INFO @ 521957457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 33802320746283707059175955052571639724396256643881445275850203795886179127806 4058
UVM_INFO @ 1598525050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 57356978275093516357533913789139533721766001981676959020397891725065583418260 7201
UVM_INFO @ 2722670518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 33613044753798908465241576727970799220800085446369597639577210805966603915346 3226
UVM_INFO @ 589298627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 97295716632177490160469799896596512619819012323537015827832754517896616097418 5743
UVM_INFO @ 385510241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 109284950375618205391864170387667147286055897838561971451274900179905120750933 109
UVM_INFO @ 33748200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 44197958761623859475960258345189052836168163469318730262279637922057705165119 7826
UVM_INFO @ 308893876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41915721776844460621859464296384156375552602666756936450218335240277901456628 8120
UVM_INFO @ 11239438941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104749795753680079023927992239589639769419202856651690377692619526654659412532 20997
UVM_INFO @ 1571328823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17000094464325165148515212776659641856511353078716434028990512796654518867962 33196
UVM_INFO @ 4652782401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 68016624117174175279474578473464589255375593585361516939380866457313826288168 5175
UVM_INFO @ 4884593691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 110582569504546123987816389745955120423337775058602577218191181605676951974116 1219
UVM_INFO @ 178908055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73632352258400710136114457999788884572059708053471955267426208829762303505977 4886
UVM_INFO @ 2585572221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 1748910466689146986822395086893489710657664551417702353726435148237324007021 9352
UVM_INFO @ 1062311979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 31796923114097284544644709509203119763715758169273492893676577794057389607664 2434
UVM_INFO @ 606529249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73516766345849607793736808438228445164806190195493350635256903914093819102263 145
UVM_INFO @ 594077712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 52865785103359537234760505115811788046689371181073271954393593536076090656669 3316
UVM_INFO @ 315669319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 67166138382625926812577014065210108647661235021684672068794198261220920087540 13140
UVM_INFO @ 18879025489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 3534240398190758399395943783663549546622443844452614085868487492743465105644 9954
UVM_INFO @ 368717543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54250490300858657895892699251518837326364203247936078185885785356202518645582 6611
UVM_INFO @ 22930915862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 48455011821286016426709076728817159716045848407519493308380168832451663560809 5416
UVM_INFO @ 206596556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8129089770679040599121614297997136698489924961957688398885849708785716139533 505
UVM_INFO @ 113545290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 60853240680291989797743218801492169005807865314970314645998889424316572402792 1838
UVM_INFO @ 528765025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33353260608967525085017207562718479096897439458624440051062367810493379076559 243
UVM_INFO @ 65963472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10685248032007673956172170930234008347429992535041302575361104140774050040569 6711
UVM_INFO @ 892908125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74994019159306934478727514672411779712031746730338582067343292607447097364568 3756
UVM_INFO @ 2467039119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43349811089967494611005735951911677279477730535308750054808770567061743669347 1509
UVM_INFO @ 12434162054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53008932733812469720066524775442305979546715615620883322312273976778123982580 8712
UVM_INFO @ 7697550078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12677647749418169564225681674223219456124965417073593295564766818368595470051 3261
UVM_INFO @ 19658141535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28385059208468052533134490561829319009814427828048272343790552634810780279036 2633
UVM_INFO @ 21490437875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2788955761431452738175780362674109002374793113222544670838676515917870396517 2463
UVM_INFO @ 16983418690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29280485836349202243102487493865529516831993046722574590052520878147175413496 3354
UVM_INFO @ 928641250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1831) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 28 test runs
otp_ctrl_stress_all_with_rand_reset 109871667388399532529208499959180125188903492525591896085173991232452345164383 9106
UVM_INFO @ 2055070426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70461376973528782776712285050772180305075817407915737208694925337744995452616 92
UVM_INFO @ 107838628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89533216544449177013409836587023610278356530236667988676735674142487549530787 7595
UVM_INFO @ 16084298572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106695652836680495198467797806841539746097757645761701806131933100308512102936 41668
UVM_INFO @ 7205661315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25084592890124109125925484196217882147460416631880937819776060543822647859244 92
UVM_INFO @ 43333947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71053503931264930328352074985906528377278447521504122647372497754241663866811 11647
UVM_INFO @ 4705484957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 543979717996310095193373174672548536693161671405547366968999787734878203123 15920
UVM_INFO @ 40043039094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83172565581516662465601159988119359895390969170302648049860122744497315562448 42751
UVM_INFO @ 1054493362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58338591387605210232901733093750922473430655006614168430001429644131977414169 146
UVM_INFO @ 5505640149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100087250036148782434268953494654060994984435256413845275196765380973678948900 16103
UVM_INFO @ 1163203127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33580646507750411554265416840429336412813462446788733087212100097117296103731 3561
UVM_INFO @ 1585475953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114507582854144926982622638810272313165812314486819453586567363004783136504645 4516
UVM_INFO @ 7270379104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86333527936867317138578614305621531872477699942313873423987993650873483535314 92
UVM_INFO @ 27408725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14384752256643954954808191143721490144862650042793720931661234417252814942262 232
UVM_INFO @ 1423289067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64169115528164596467028682982267651234333769132685898320661024162167028659603 15528
UVM_INFO @ 358805983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7549848870334039258373615563519675525861578481337677051745286799670713169280 16446
UVM_INFO @ 970007927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91240178493420630522021490417891933063872165508668223935525049756755811137828 19650
UVM_INFO @ 4777753689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90151798888383392259455284305144481698331355107151494362103629932978501714884 1225
UVM_INFO @ 141927252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44934444225046137506322075035300417318350529418596329552114132731457016394785 1452
UVM_INFO @ 2240899782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5535202712512647470657421702393958461313836060953213034584288906826222334470 2961
UVM_INFO @ 5449861339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8874192586392986152304898272173918877928564395682003933244985062289950481888 9085
UVM_INFO @ 868245569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27837428302008606954010825417968528687128001379683198454599676169764228273199 61352
UVM_INFO @ 3778051761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5837003261570186695575002553576896784271377722107180090425240346473933073046 92
UVM_INFO @ 103791123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47182971036203819354496925411732424257130128973924923609404018437280721991451 92
UVM_INFO @ 31803170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50027327973259789950208383558598031511871870565592478306406391149882599168197 14338
UVM_INFO @ 1607033614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57529339072977705240267722376049468885853564052090982565436081615790388658902 92
UVM_INFO @ 26198107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95876590933990436359204289350342198825726924751900168922409136657409059719520 1807
UVM_INFO @ 889896849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17047670327415913872003960804041023816414741219926514928387284691015127027523 7725
UVM_INFO @ 2708103159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 15 test runs
otp_ctrl_stress_all_with_rand_reset 113224621039233820381272712684462629364333620551788790535257551426417625914118 3431
UVM_INFO @ 1836311721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112697024916502640110614702428959896620136345074440541302733230820187003863518 4067
UVM_INFO @ 13480852846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23447344669885152937340049375318261243352869273614095648311595930593638136340 2072
UVM_INFO @ 4985977760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84987631872463152862533045589233590607921304905050937969878441557861172674173 52441
UVM_INFO @ 12524585384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59459685987205222910847454889724394213521800182749945663166593040876255257011 109
UVM_INFO @ 30239973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2330480733170767158681428421243385634032643823604921583251785469047377723264 7220
UVM_INFO @ 6243498533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 862876482984831925739892825810391218988295407668009120068890586962958668769 5236
UVM_INFO @ 510856515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100495622923552153142872268194949719536626304716100641139458605217659685786405 3306
UVM_INFO @ 1146179215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23230709849826488809961931851663309718230944265635913022577511579300640827369 3704
UVM_INFO @ 11419357901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111015878038815430572950372127436022660584234449887829306690493602794731145967 7506
UVM_INFO @ 1036726074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103667480194758350679197117607315839057014882775546579804407430121691658947874 10612
UVM_INFO @ 8113442644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69692233068708373900047048970314005517642453400369071853741370602647307235545 4246
UVM_INFO @ 2729792689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77243684255545512196363684067720382126001893964651377405875949254622605045800 10962
UVM_INFO @ 3294992202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15639603370546063103082910661853749760988139146615129303433771677632306664637 2305
UVM_INFO @ 1497587195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95178991398493480135164328984682510181581347947209417298603434580199388655725 14162
UVM_INFO @ 4993451468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 10 test runs
otp_ctrl_stress_all_with_rand_reset 25453499114637634661314422080087586311425577161030836015316238547638117573627 92
UVM_INFO @ 65299155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14875902380825863995643027485596157717691952832744046200687660477687125988005 2892
UVM_INFO @ 1822241180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28547338696531538554786074327764903514944841188051279269040973826708728247154 186
UVM_INFO @ 1321101532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25324625084753949422603878336996017178628033140434462321533590485323990636966 92
UVM_INFO @ 26732143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95372329290308678077454907009090129636753212376562184856976716015565595218551 93
UVM_INFO @ 70837808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35094653811177730803004155683934883083904959788233732083636595039882426774406 60994
UVM_INFO @ 54557898139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40448796634666768368751990390211654132352838428520065944964690009994261847997 8211
UVM_INFO @ 965717412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104086521998144112068234643059709102050877081921440987303845165416594907166283 92
UVM_INFO @ 55982763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43961355677367086453497647975473002157975703592896360929969101668095563090878 408
UVM_INFO @ 5061541108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46210818344856692767532768112159601018332582400721909479177713157703534720680 8790
UVM_INFO @ 5773156247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 3 test runs
otp_ctrl_stress_all_with_rand_reset 73670738822646733487182930044557860302611010011091522277597604634254496557215 9779
UVM_INFO @ 11429011284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51505836812703082411087562873062918485071152826976736796592384178894167721683 1235
UVM_INFO @ 10994486860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41087090468902207638827754367280448796282557194066271910465475018119401758426 284
UVM_INFO @ 10073885206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:283) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 68227768589922943120847991810955846810941313124532049649821828454202439447618 6907
UVM_INFO @ 10535993291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_parallel_lc_req 48276937963330940293609666943612781182249898503515550474316058621394319132378 10813
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *b* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 35673991610334605090630908767235618391762042306295125014381192944452051297046 9053
UVM_INFO @ 58921462278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:206) [scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 110628946364167174140026324091715070521247476134886956070059646182804019819352 1963
UVM_INFO @ 467914843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 67835788025990237367318402096105670976314971402239460454345119558146433237081 93
UVM_ERROR @ 102967930 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 102967930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 1497109611285364530470171676236616486050475149680047229273797584791580018958 6338
UVM_INFO @ 14892300150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 78376754623339812029248557746921705159424663578070056159806364962564560056198 12682
UVM_INFO @ 18308350014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 79689676005541869870870681680090421749985909553398368798684227637790175605098 9999
UVM_INFO @ 16184655534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---