Simulation Results: pwrmgr

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.34 %
  • code
  • 97.57 %
  • assert
  • 98.43 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.75 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
94.16%
V2S
100.00%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.920s 28.205us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.760s 22.748us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.980s 24.336us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.960s 1414.404us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.960s 53.279us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.210s 60.069us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.980s 24.336us 5 5 100.00
pwrmgr_csr_aliasing 0.960s 53.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.200s 259.865us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.200s 259.865us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 0.970s 70.581us 10 10 100.00
pwrmgr_lowpower_invalid 0.900s 42.631us 10 10 100.00
reset 17 20 85.00
pwrmgr_reset 1.280s 1000.000us 8 10 80.00
pwrmgr_reset_invalid 1.050s 103.762us 9 10 90.00
main_power_glitch_reset 8 10 80.00
pwrmgr_reset 1.280s 1000.000us 8 10 80.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.240s 330.399us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.180s 441.572us 10 10 100.00
disable_rom_integrity_check 8 10 80.00
pwrmgr_disable_rom_integrity_check 2.150s 1000.000us 8 10 80.00
stress_all 7 10 70.00
pwrmgr_stress_all 14.990s 11008.426us 7 10 70.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.890s 47.330us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.350s 91.873us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.350s 91.873us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.760s 22.748us 1 1 100.00
pwrmgr_csr_rw 0.980s 24.336us 5 5 100.00
pwrmgr_csr_aliasing 0.960s 53.279us 1 1 100.00
pwrmgr_same_csr_outstanding 1.140s 68.741us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.760s 22.748us 1 1 100.00
pwrmgr_csr_rw 0.980s 24.336us 5 5 100.00
pwrmgr_csr_aliasing 0.960s 53.279us 1 1 100.00
pwrmgr_same_csr_outstanding 1.140s 68.741us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.770s 165.762us 25 25 100.00
pwrmgr_sec_cm 1.530s 952.185us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.530s 952.185us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.530s 952.185us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.770s 165.762us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.100s 889.815us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.240s 330.399us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.300s 851.879us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.940s 247.151us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.800s 38.009us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.530s 952.185us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.530s 952.185us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.530s 952.185us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.770s 59.938us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.800s 41.928us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.240s 231.970us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.980s 24.336us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.980s 24.336us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 2 10 20.00
pwrmgr_escalation_timeout 0.930s 338.492us 2 10 20.00
stress_all_with_rand_reset 9 10 90.00
pwrmgr_stress_all_with_rand_reset 14.410s 18685.178us 9 10 90.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 8 test runs
pwrmgr_escalation_timeout 20035320862473844089049867536106781021668058649293081153507919026692080541246 79
UVM_ERROR @ 189062305 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 189062305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 80605739654517609482217915462025204460258778366335289937743767619621607484835 79
UVM_ERROR @ 386176677 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 386176677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 23398305341089585574487973350811424361807722980217978505710333348055068322969 79
UVM_ERROR @ 795160674 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 795160674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 110691319765421403753015859317063536970522184270516757145724390469047373127924 79
UVM_ERROR @ 184760816 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 184760816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 96357876241433604928929326033881290788033772776315337279574398001890805177901 79
UVM_ERROR @ 368153394 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 368153394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 97269329773588659079150862409849160513221119917220438353128882312803237525514 79
UVM_ERROR @ 371494224 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 371494224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 17928020385986927900714161796215464279146326043800851060097557769296673470606 79
UVM_ERROR @ 356597130 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 356597130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 7621582363297885875862187857869124410151920984925910694311332345220213334604 79
UVM_ERROR @ 518524411 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 518524411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_disable_rom_integrity_check 7048159887225168556208336222844995795433021636280670610377164026343313302264 96
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 112451848008653141076328224183061482736502841450417423779650876043191089525976 119
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 99881443327109038041892877740188820837704473616961506662485782186255688960208 86
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 60851776900098612647037687431692348005605650461747372972786268423724075129879 90
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 3 test runs
pwrmgr_stress_all 107811793722530590118570860574907124772684283301260433694540156802575301530500 324
UVM_INFO @ 10441534682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 107350880330558915365972083336403049561277019827936387357383677434546704664003 437
UVM_INFO @ 11008425969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 29657497790306887231444068089106952439138116763350692447387873489233941973796 816
UVM_INFO @ 11502317977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitRomCheck 1 test run
pwrmgr_reset_invalid 46664846750525953105749899173293833700541346418026140693669055105212840121494 140
UVM_INFO @ 124438019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
pwrmgr_stress_all_with_rand_reset 19278942559712102815238116217382875135821647184314486508819018190291264196319 1726
UVM_INFO @ 5078422910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---