| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| rstmgr_smoke | 1.630s | 300.787us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 0.980s | 150.648us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.040s | 87.694us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 8.370s | 2841.224us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 1.390s | 234.031us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 1.330s | 208.068us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rstmgr_csr_rw | 1.040s | 87.694us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 1.390s | 234.031us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 5 | 5 | 100.00 | |||
| rstmgr_por_stretcher | 1.070s | 198.401us | 5 | 5 | 100.00 | |
| sw_rst | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst | 2.610s | 582.111us | 5 | 5 | 100.00 | |
| sw_rst_reset_race | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 1.090s | 157.439us | 5 | 5 | 100.00 | |
| reset_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 5.320s | 1776.915us | 5 | 5 | 100.00 | |
| cpu_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 5.320s | 1776.915us | 5 | 5 | 100.00 | |
| alert_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 5.320s | 1776.915us | 5 | 5 | 100.00 | |
| reset_info_capture | 5 | 5 | 100.00 | |||
| rstmgr_reset | 5.320s | 1776.915us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| rstmgr_stress_all | 63.570s | 15371.865us | 5 | 5 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rstmgr_alert_test | 1.010s | 88.702us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 3.560s | 654.329us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 3.560s | 654.329us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 0.980s | 150.648us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.040s | 87.694us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 1.390s | 234.031us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.450s | 253.110us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 0.980s | 150.648us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.040s | 87.694us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 1.390s | 234.031us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.450s | 253.110us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rstmgr_sec_cm | 25.490s | 21632.167us | 5 | 5 | 100.00 | |
| rstmgr_tl_intg_err | 3.060s | 917.672us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 25.490s | 21632.167us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 25.490s | 21632.167us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rstmgr_tl_intg_err | 3.060s | 917.672us | 25 | 25 | 100.00 | |
| sec_cm_scan_intersig_mubi | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.430s | 197.441us | 5 | 5 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 25 | 25 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 8.680s | 2560.629us | 25 | 25 | 100.00 | |
| sec_cm_leaf_rst_shadow | 5 | 5 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 1.430s | 302.244us | 5 | 5 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 25.490s | 21632.167us | 5 | 5 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.040s | 87.694us | 5 | 5 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.040s | 87.694us | 5 | 5 | 100.00 | |