| V1 |
|
100.00% |
| V2 |
|
85.83% |
| V2S |
|
100.00% |
| V3 |
|
42.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.830s | 143.704us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.860s | 13.277us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.820s | 16.375us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.050s | 311.066us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.930s | 136.228us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.350s | 44.262us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.820s | 16.375us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 0.930s | 136.228us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 8.860s | 37899.750us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.200s | 987.668us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 590.700s | 1631648.075us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 590.700s | 1631648.075us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 6.440s | 3876.673us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.860s | 12.449us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.870s | 73.490us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.350s | 81.546us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.350s | 81.546us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.860s | 13.277us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.820s | 16.375us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 0.930s | 136.228us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.150s | 20.177us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.860s | 13.277us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.820s | 16.375us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 0.930s | 136.228us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.150s | 20.177us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.260s | 91.093us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.740s | 112.037us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.740s | 112.037us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 3 | 10 | 30.00 | |||
| rv_timer_min | 1.130s | 1517.173us | 3 | 10 | 30.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.350s | 105.292us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 14 | 20 | 70.00 | |||
| rv_timer_stress_all_with_rand_reset | 53.520s | 6102.194us | 14 | 20 | 70.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 25 test runs | |||
| rv_timer_min | 55141607565373930172945741367131706199369543803577880662342302665573546873985 | 77 |
UVM_INFO @ 70999693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 39757689640785692353618860355684045203226382462762908428282471231819887429744 | 76 |
UVM_INFO @ 7475387225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 107707843293899118280973288744545396909479215562395292912115502537732613599483 | 76 |
UVM_INFO @ 54147853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 9060736640736183255812870105203788826974343687362033554887651889397015398070 | 75 |
UVM_INFO @ 252180451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 92631176034931274030450296100877529383452571872140032254346557882722317299496 | 76 |
UVM_INFO @ 1517172550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 102388791808610039290026997966468290763950229536442223388961498079022948207408 | 75 |
UVM_INFO @ 222462303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 92755295418267914205778340414002200603172288884547795007010649872456395355781 | 76 |
UVM_INFO @ 1514428644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 61262338729807023337304064836807725065849178306020890820550567280186084077533 | 75 |
UVM_INFO @ 105754478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 79705498576560445941093153687742071176701131507133622064984100911390863070116 | 75 |
UVM_INFO @ 896343765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 42396693278944129295564082516802736325791859973433557370632624260035010921100 | 75 |
UVM_INFO @ 658017631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 26859859666875315203185151342827139896888231845225134630910130149339663366115 | 78 |
UVM_INFO @ 231226252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 19045831352267330099180071159325233398962955550336825923972314106782189682269 | 75 |
UVM_INFO @ 127043165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35015300460413731554082934216112820611698856617546633552127101011925867821428 | 75 |
UVM_INFO @ 255471801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 68601914622066467005570834436359790110262738071171073162633279282429041235735 | 77 |
UVM_INFO @ 75072539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 70590299009610128441809268344667396055994186828037780756615169092045425803860 | 75 |
UVM_INFO @ 37899749899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 25297130830178641186625757147294481168126041767959921700901940237044861062158 | 75 |
UVM_INFO @ 253241251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 33863060485664776752659030865306891500840770265496014111606237883508152628633 | 75 |
UVM_INFO @ 243613012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 66811321290910909864526490865009925692783807182736650177701098257071875094544 | 75 |
UVM_INFO @ 105747551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 83619156676888716208867374028582566336691617899243009631355300327445384425350 | 76 |
UVM_INFO @ 1616860325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 114625583579637281242694463947404107173505325772972011336066221556429153166587 | 77 |
UVM_INFO @ 329325091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 66738589280203292724014841962196314981197767019275692615690238210422559540783 | 76 |
UVM_INFO @ 1820170855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 5761401452900275730492080282127067275019100615602829939849165071291997400237 | 76 |
UVM_INFO @ 820469517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 51237303325698907599685753527092037115855570345365297867494254718123459600525 | 75 |
UVM_INFO @ 1235863449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 76359745175495947287557793809785366607361442810157345415298968421801463150958 | 75 |
UVM_INFO @ 1105670665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 60094202649424874339510120522064446608090949478045198528580667815831857949070 | 75 |
UVM_INFO @ 377425576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| rv_timer_max | 89856532450851349556906165065531047531510698921758194291278399167574978370867 | 75 |
UVM_INFO @ 567486476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 95650425591187171123287208774386459424329110278868680719416337696575341873663 | 75 |
UVM_INFO @ 160781242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 21932645169661642422437989462163913430442242407120782982853334171115427716609 | 75 |
UVM_INFO @ 107784482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 56044633369515800504541113660182564490705911920295667669944420057463785622505 | 75 |
UVM_INFO @ 83077413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 75106889769987761813775859930344214669335217284665296699611131430636259027894 | 75 |
UVM_INFO @ 177624381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 97679832006430159420694126904990522302433954644506937959163519810500157675570 | 75 |
UVM_INFO @ 178355942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 41722930934927283018931384894445023202344980778535196831896242456037363876178 | 75 |
UVM_INFO @ 105291952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 110151647701156462151279176181518990634500367437630299356744525588840553805708 | 75 |
UVM_INFO @ 172615988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 479466751636313690706805004234331135346476392759755853671905144040282820611 | 75 |
UVM_INFO @ 94309083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 4 test runs | |||
| rv_timer_stress_all_with_rand_reset | 52337751028449348474215926995566332487657499067922259275366869356346806581523 | 256 |
UVM_INFO @ 5839653238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 33932352728013394950240746564501085165049847558481988215204803968283291323116 | 79 |
UVM_INFO @ 9170977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 48422167735928337132365554671115582244840986866945976851728391274299412617410 | 260 |
UVM_INFO @ 3449356298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 62972207694563761568331600630300904903215289753837333031180449539053618631051 | 115 |
UVM_INFO @ 1321147376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 52137183812507768864408013716624202775253101135717137805329748183240305094564 | 150 |
UVM_INFO @ 1235047879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 60677816327310004961661655454015149171413421521550410387869606012059372577394 | 161 |
UVM_INFO @ 1867492233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | 1 test run | |||
| rv_timer_max | 15765268946642217401789458962796395061211258181267132433228792656294158035368 | 75 |
UVM_INFO @ 531721214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|