Simulation Results: spi_host

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.88 %
  • code
  • 91.30 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 39.000s 1435.709us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.730us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 15.469us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 679.064us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 84.462us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 26.185us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 15.469us 5 5 100.00
spi_host_csr_aliasing 1.000s 84.462us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.580us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 85.711us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 24.993us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 12.000s 1292.962us 10 10 100.00
spi_host_error_cmd 2.000s 80.542us 10 10 100.00
spi_host_event 120.000s 206786.866us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 7.000s 348.758us 10 10 100.00
speed 10 10 100.00
spi_host_speed 7.000s 348.758us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 7.000s 348.758us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 365.000s 200000.000us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 102.000s 2619.662us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 69.906us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 7.000s 348.758us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 7.000s 348.758us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 39.000s 1435.709us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 39.000s 1435.709us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 37.000s 1456.992us 10 10 100.00
spien 10 10 100.00
spi_host_spien 21.000s 2059.172us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 129.000s 5196.624us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 5.000s 2568.354us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 12.000s 1292.962us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 36.277us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 23.011us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 532.695us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 532.695us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 17.730us 1 1 100.00
spi_host_csr_rw 2.000s 15.469us 5 5 100.00
spi_host_csr_aliasing 1.000s 84.462us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.093us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 17.730us 1 1 100.00
spi_host_csr_rw 2.000s 15.469us 5 5 100.00
spi_host_csr_aliasing 1.000s 84.462us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.093us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 99.133us 25 25 100.00
spi_host_sec_cm 2.000s 267.404us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 99.133us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 42150289559053250746327212638239167970367546704731393678890210983805583831752 115
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---