Simulation Results: sram_ctrl/main

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.85 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
97.30%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 8.000s 2802.708us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 47.235us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.044us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 225.496us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.677us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
sram_ctrl_csr_mem_rw_with_rand_reset 12.000s 10002.042us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 18.044us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.677us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 323.000s 53674.006us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 122.000s 21729.398us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 47.000s 15349.692us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 227.000s 16131.033us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 200.000s 60562.697us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 75.000s 65188.902us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 42.000s 35892.719us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 66.000s 24705.773us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 7.000s 728.911us 8 8 100.00
sram_ctrl_partial_access_b2b 347.000s 23492.617us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 2537.479us 0 8 0.00
sram_ctrl_throughput_w_partial_write 9.000s 11004.543us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 684.395us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 19.000s 2407.726us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 2412.051us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 706.000s 119796.402us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 16.070us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 151.614us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 151.614us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 47.235us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.044us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.677us 1 1 100.00
sram_ctrl_same_csr_outstanding 3.000s 53.388us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 47.235us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.044us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.677us 1 1 100.00
sram_ctrl_same_csr_outstanding 3.000s 53.388us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7260.227us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 6.000s 2597.216us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 434.496us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 2597.216us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 434.496us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 19.000s 2407.726us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 19.000s 2407.726us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.044us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 66.000s 24705.773us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 66.000s 24705.773us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 66.000s 24705.773us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 42.000s 35892.719us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 683.248us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7260.227us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 11.000s 13347.408us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 8.000s 2802.708us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 8.000s 2802.708us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 66.000s 24705.773us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 2597.216us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 42.000s 35892.719us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 2597.216us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 2597.216us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 8.000s 2802.708us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 2597.216us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 40.000s 5082.661us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 98043722246872268685116196982758545717381872282345564938182116816862065109851 86
UVM_INFO @ 2642568855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 99675993267007119816765963464032668833756289645581841193331747416536733400336 86
UVM_INFO @ 2751538275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 35842422892584088325861070658769789755377988421653319209140070696534064751857 86
UVM_INFO @ 2537478585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 39746973116617961076600272028297026626039587238469998755489263767294777285009 86
UVM_INFO @ 2737386584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 26147204915289873764500301609884085646063430201330088078542060805689696833408 86
UVM_INFO @ 677472299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 72637252518746224854098373114097649148374562752651985645311067405528427905701 86
UVM_INFO @ 668421540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 8785651674505024100694426134030492121492807128970303282523437469751788440360 86
UVM_INFO @ 694262293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 2742196983084239893372111876380136900579041883828518543395340474689022058666 86
UVM_INFO @ 682674051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 76193367086857379748324103396044684772029805892795428768761452743102989855084 86
UVM_INFO @ 943631082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 60680274411038980000869875930955420064859942364311841314100871821957732244650 86
UVM_INFO @ 1348744551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 79285319910050591110562232063865594616893062410478267360143549041047508337171 86
UVM_INFO @ 1294281097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 24674029671456565548816685679694225869291017111443736200616856743187620999984 86
UVM_INFO @ 695444966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 36225793435809420332927212233028944458707997798480896355091858965267805337932 86
UVM_INFO @ 2434921559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 40562685271504687259304521389092399569521572361529493457660216659071305539568 86
UVM_INFO @ 11004542691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 18665384669084002737076912267779172564386342734570587825542068257236671754175 86
UVM_INFO @ 5496130162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 54488865075910906102357015824403302521574064306705221723432459996896468154098 86
UVM_INFO @ 2528176331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 14064016201415670776083529194496437720374879868431454297902077649831849181920 86
UVM_INFO @ 696960284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 94675009418020835022293987768436573430103738203897423026340451344749455793974 86
UVM_INFO @ 1413771486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 86355579163505783708697059217515400416219102545883976121048064950367113474003 86
UVM_INFO @ 2758592873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 80783311668829099969974463805544313549903161047509900143274584857981080801848 86
UVM_INFO @ 1346560946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 46365701656614799599427984268072998970665681180976751570195968782912144889323 86
UVM_INFO @ 690983768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 46076550658759358810812469101353555279330038241432163337184623970711617754348 86
UVM_INFO @ 684394781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 84838166697552245397549916907861452970706494876976153252453158318291393464590 86
UVM_INFO @ 677196819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 68252626345180353987221236348376616962935257933728189150791167476777049441212 86
UVM_INFO @ 2765907671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 92175777565635388148546365579948734527253370257821745138762836762621511644459 85
UVM_INFO @ 10002041906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---