Simulation Results: sram_ctrl/ret

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.51 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 233.649us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 69.081us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 31.638us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 2928.545us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.184us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 157.532us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 31.638us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 15.184us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 11.000s 3374.744us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 6.000s 192.239us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 14.000s 19836.338us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 250.000s 4294.910us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 9.000s 898.554us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 34.000s 8154.959us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 7.000s 4210.126us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 13.000s 776.871us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 1262.396us 8 8 100.00
sram_ctrl_partial_access_b2b 321.000s 93807.893us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 93.556us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 51.261us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 73.771us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 13.000s 4443.901us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 30.795us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 74.000s 74533.162us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 23.494us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 260.449us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 260.449us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 69.081us 1 1 100.00
sram_ctrl_csr_rw 2.000s 31.638us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 15.184us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.452us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 69.081us 1 1 100.00
sram_ctrl_csr_rw 2.000s 31.638us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 15.184us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.452us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 374.943us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 4.000s 2379.909us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 1372.938us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 2379.909us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 1372.938us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 4443.901us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 4443.901us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 31.638us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 13.000s 776.871us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 13.000s 776.871us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 13.000s 776.871us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 7.000s 4210.126us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 146.215us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 374.943us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 43.982us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 233.649us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 233.649us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 13.000s 776.871us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 2379.909us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 7.000s 4210.126us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 2379.909us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 2379.909us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 233.649us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 2379.909us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 107.000s 2447.353us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 44546240549641020198828715257570338172332125123247112567685002186753569388251 86
UVM_INFO @ 93555885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 93601568086545590750259447059536583677475995275356298639597497347185031623003 86
UVM_INFO @ 220963626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 92959030516976650630123416131512267917507057269997342714557251454342460443514 86
UVM_INFO @ 93785665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 109031856580849918104891372588541776829705661806219777561438385732067013404659 86
UVM_INFO @ 51261100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 68749372193884139811576025857071502307140640906070743514744053180759387306709 86
UVM_INFO @ 105608353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 80114993266925264489073558282193306476808023502738485541979228444666053549591 86
UVM_INFO @ 52477085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 102144149610495854533604320082904900714823685279704642170906509815553815501087 86
UVM_INFO @ 138286761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 46072881059539018012199398751340661399270963063730548837231090349746176001463 86
UVM_INFO @ 227261910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 109892069029704797942306571737267044432912407464577931376423997047580301895597 86
UVM_INFO @ 52354468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 20199632608108466313691323491348600779782632702358728148520304568436155532035 86
UVM_INFO @ 106057720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 43031202448324475667224864514021768751748648086993632994098090704113005553587 86
UVM_INFO @ 105294512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 20349428515722917998642772880981086417429444753281618651376589872154606791404 86
UVM_INFO @ 32432436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 19625177590414394190938631655505521703745567855381375660092887981276176489565 86
UVM_INFO @ 26622435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 38229012177779795822376979120479819934774849766810510248634148853934079147205 86
UVM_INFO @ 24108255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 50431923605901118159115058138598206548443116776204723731211074578793339348178 86
UVM_INFO @ 31644082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 7928148121109655729326437961470578985328806240191950960682184772580094303477 86
UVM_INFO @ 54216425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 55634180948991374842503758265888125786621012082949409304280255963992206125688 86
UVM_INFO @ 73770623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 67096415843008516489595393183031592748294827718475399776064875031125088988814 86
UVM_INFO @ 58534147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 61456502487036911698103730978810432433729358646883802000306289498503273393787 86
UVM_INFO @ 55225774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 24779307809782281454958330004267474706707740063055427836143545943032504974704 86
UVM_INFO @ 34965654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 8328878939613214842619622258731126105706181601045451592137772008942887917062 86
UVM_INFO @ 154632895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 15590371182994385863856883249013648301571903982733053228347874160996200518269 86
UVM_INFO @ 29580220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 39889023670312124111605054794952335974980578286007257236420292554538961121390 86
UVM_INFO @ 163796996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 25289728216510086960063486551631570874666726540347044016411849366117523546583 86
UVM_INFO @ 44601717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---