Simulation Results: uart

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.88 %
  • code
  • 92.64 %
  • assert
  • 98.56 %
  • func
  • 99.44 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
96.98%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 7.820s 5684.384us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.900s 55.862us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.980s 53.224us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.380s 82.346us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.110s 22.691us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.450s 27.192us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.980s 53.224us 5 5 100.00
uart_csr_aliasing 1.110s 22.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 166.620s 138927.416us 10 10 100.00
parity 20 20 100.00
uart_smoke 7.820s 5684.384us 10 10 100.00
uart_tx_rx 166.620s 138927.416us 10 10 100.00
parity_error 20 20 100.00
uart_intr 114.780s 400882.686us 10 10 100.00
uart_rx_parity_err 130.560s 280448.603us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 166.620s 138927.416us 10 10 100.00
uart_intr 114.780s 400882.686us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 372.540s 126053.501us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 153.170s 94118.547us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 529.640s 310272.109us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 114.780s 400882.686us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 114.780s 400882.686us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 114.780s 400882.686us 10 10 100.00
perf 10 10 100.00
uart_perf 499.570s 17016.609us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 10.340s 5333.584us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 10.340s 5333.584us 10 10 100.00
rx_noise_filter 0 10 0.00
uart_noise_filter 32.070s 18781.869us 0 10 0.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 62.400s 45319.183us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 16.730s 16577.141us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 41.910s 6280.523us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 635.230s 144143.436us 10 10 100.00
stress_all 8 10 80.00
uart_stress_all 1089.800s 207400.564us 8 10 80.00
alert_test 10 10 100.00
uart_alert_test 0.970s 15.960us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.960s 28.346us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.470s 53.371us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.470s 53.371us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.900s 55.862us 1 1 100.00
uart_csr_rw 0.980s 53.224us 5 5 100.00
uart_csr_aliasing 1.110s 22.691us 1 1 100.00
uart_same_csr_outstanding 1.170s 111.653us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.900s 55.862us 1 1 100.00
uart_csr_rw 0.980s 53.224us 5 5 100.00
uart_csr_aliasing 1.110s 22.691us 1 1 100.00
uart_same_csr_outstanding 1.170s 111.653us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.300s 74.412us 5 5 100.00
uart_tl_intg_err 1.750s 195.205us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.750s 195.205us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 65.150s 4093.308us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 6 test runs
uart_noise_filter 45911973983716404566254431933598805738914977070692709558417371858968806681282 77
UVM_ERROR @ 24247771822 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 24247891822 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (158 [0x9e] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 25466691822 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 25466691822 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 4825322610534606867529743054415519308140509799959446183761744126889437616029 77
UVM_ERROR @ 9002788244 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 9002829911 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 9032163479 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9032163479 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
uart_noise_filter 9525129173016487187387911193730352908626458258528796355482731209533173969632 75
UVM_ERROR @ 2272421550 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2272458587 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (246 [0xf6] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2272532661 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2272569698 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (246 [0xf6] vs 223 [0xdf]) reg name: uart_reg_block.rdata
uart_noise_filter 27829040294633886737891459281116371430748940922712171763602331518236836518155 76
UVM_ERROR @ 1729838340 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1730022012 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (133 [0x85] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1766368660 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1766368660 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 31045837078371218554381649698896431431177505448534998856394699420876195088133 74
UVM_ERROR @ 721076452 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 721176452 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 721376452 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 721476452 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
uart_noise_filter 28902823937279573257371160884322190683776868590238416845411272074780669626623 76
UVM_ERROR @ 31548444981 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 31548484981 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (234 [0xea] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 31548564981 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 31548604981 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (234 [0xea] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 6 test runs
uart_stress_all 70850209743344804518218816594001979783522200848510545696324029866163995385870 171
UVM_ERROR @ 162516457602 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 162516457602 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 162533679807 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 162533679807 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 87628764997445030775004967282229790233163594738653374057239198720961141947510 75
UVM_ERROR @ 1226096692 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1233638600 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 1233638600 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1233846940 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
uart_noise_filter 28471703449206571220885474677383099047151668859808424399763438143405342821501 84
UVM_ERROR @ 17203638590 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 17249088590 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 17249088590 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 17261568590 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
uart_noise_filter 81324310490715938183348436983655131910265187218625486523136643974787159951473 76
UVM_ERROR @ 22009442325 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 23158800477 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 23158800477 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 23422777957 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
uart_stress_all 98949446241387034944509485206406094776778538088443123852109525207459713764125 104
UVM_ERROR @ 150772561345 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 150772622569 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 150773408277 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 150774163373 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 55969293972030872782334183005135573473816664252483477721331108701479919513220 107
UVM_ERROR @ 1910205382 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 2285765382 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/558
UVM_INFO @ 2505605382 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/558
UVM_INFO @ 2870445382 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/558
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 2 test runs
uart_noise_filter 49181897308620474356428959924194185235833772579336067964009788490706038739725 77
UVM_ERROR @ 13438634000 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 13484348418 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 13484369470 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 13484379996 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
uart_stress_all_with_rand_reset 59232315670553621523094833279917514699088060139265190930764587301987840392318 153
UVM_INFO @ 10622799280 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/156
UVM_INFO @ 11003885662 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 11/156
UVM_ERROR @ 11086511323 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 11086511323 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0