Simulation Results

Simulation Results: adc_ctrl

01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.28 %

code
95.57 %

assert
92.54 %

func
13.74 %

line
98.80 %

branch
97.28 %

cond
87.43 %

toggle
99.76 %

FSM
94.59 %

Validation stages

V1		100.00%
V2		49.15%
V2S		100.00%
V3		10.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	15.760s	5864.742us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.650s	1214.436us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	2.310s	547.831us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	52.850s	26982.644us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	2.360s	811.422us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.600s	597.431us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	2.310s	547.831us	5	5	100.00
	adc_ctrl_csr_aliasing	2.360s	811.422us	1	1	100.00

87/177 passed

49.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.050s	445.091us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	1.970s	366.018us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	1.760s	341.941us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.120s	467.088us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	1.740s	321.060us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	1.800s	422.317us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	1.830s	428.511us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.150s	510.837us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	13.800s	5286.666us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	75.970s	43506.504us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	220.190s	126115.786us	10	10	100.00
stress_all				0	10	0.00
	adc_ctrl_stress_all	270.550s	124477.521us	0	10	0.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.260s	501.853us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.090s	424.806us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	4.060s	548.274us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	4.060s	548.274us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.650s	1214.436us	1	1	100.00
	adc_ctrl_csr_rw	2.310s	547.831us	5	5	100.00
	adc_ctrl_csr_aliasing	2.360s	811.422us	1	1	100.00
	adc_ctrl_same_csr_outstanding	17.160s	4411.129us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.650s	1214.436us	1	1	100.00
	adc_ctrl_csr_rw	2.310s	547.831us	5	5	100.00
	adc_ctrl_csr_aliasing	2.360s	811.422us	1	1	100.00
	adc_ctrl_same_csr_outstanding	17.160s	4411.129us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	15.790s	8054.120us	5	5	100.00
	adc_ctrl_tl_intg_err	24.990s	8182.723us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	24.990s	8182.723us	25	25	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	adc_ctrl_stress_all_with_rand_reset	10.000s	15502.405us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				99 test runs
	adc_ctrl_filters_polled	7216772852439497592883864290565783640901531882650392309971366297826473635771	386	UVM_INFO @ 329721668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	43556527354798804511072664350415598136797574412077529897418811199253459016880	386	UVM_INFO @ 470550906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	16903619531085989553627755301208911549346865197981470730453881360293795438417	386	UVM_INFO @ 409697435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	41210808954836802307440940049335970327238161514302479150176344620405184009121	386	UVM_INFO @ 355412064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	49190766682241589742663910753876936029327981077463766769165340884857642376170	386	UVM_INFO @ 489909559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	81968446266442830620603070233807079954393479961624877793896960963322129693589	386	UVM_INFO @ 409050978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	24124086314127035048694955307817002495303702456019383598411005266429359447972	386	UVM_INFO @ 450915579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	70734068501193471059506515665130625673508036145715767739480775640364255407585	386	UVM_INFO @ 397592263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	38269497238087706033354384943382313476987074013224853583931354635511744108440	392	UVM_INFO @ 849718755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	89348126129344151245249859250464592059956319746902043858346130592016905512000	414	UVM_INFO @ 104230118002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	43639530663318137694866113359486081335984763091653691764515682439644746268843	386	UVM_INFO @ 487732559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	90197938827631145563217898676022921825958983327810808483887161997461936586971	386	UVM_INFO @ 318702782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	95391528281332488125060998363796680873599500442347856383766395896358415223328	386	UVM_INFO @ 341941391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	37993028001843569248786888651466543937659717645257379044512174293161059615031	386	UVM_INFO @ 333067005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	29179451533726463620439650054967242693717335820149602875956669314570551807427	386	UVM_INFO @ 432155992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	70021321406678691381296917577377527688736734633688227981119298481791047194884	386	UVM_INFO @ 463844006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	108308762750780097393700050048412651710722922057426583602670526665048616963128	386	UVM_INFO @ 457969675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	91473142176242996321168014295410947065708891494107788812698838348647887398113	386	UVM_INFO @ 451844340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	11546366152635065046497937517662908828833623239760414539195022568893759480337	446	UVM_INFO @ 11120393143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	86239747321846313516877900516985077439622486666201517415007247132248129865859	387	UVM_INFO @ 541409457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	37792791293749135696591953170938181162606666237562999896736423566733287741181	386	UVM_INFO @ 368694928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	31901790869795252739805854594359540661821724829183024722172667380321996968321	386	UVM_INFO @ 371792157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	37159265117139281740607237544684044711649747994867583823217890536552080277978	386	UVM_INFO @ 375444230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	88360726542393218039595212079979918071610322345318717929169084634801508575377	386	UVM_INFO @ 504401801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	79588884436425217065843702267853890763713897571575683826267763531475494741180	386	UVM_INFO @ 337641506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	24465998088869755894728561811847872551541678212067761676144334911761534091445	386	UVM_INFO @ 347013277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	58472849260654847517300297928849983456934043207882386913281827747612429101971	386	UVM_INFO @ 360251489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	51701199973327347764094514194759258975427539215061249123398944564844556048370	386	UVM_INFO @ 321873357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	75799181961279366849444341725347630741113665070827889886763557254042849572614	399	UVM_INFO @ 742286905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	4282959853148410840922339606934680350529657696344727185414119309870759752581	387	UVM_INFO @ 830177788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	10307612372265780370246264088761073620063685939095210074944160161014282681711	386	UVM_INFO @ 423377902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	43572268917075150021570868844605622309669223789411646442649716116370572066342	386	UVM_INFO @ 409861293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	35024790286595788765967267949308490672966944344041164580352802940459879992708	386	UVM_INFO @ 396519720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	67874522016322037866048027786459705119489854090994865989980355716885692761565	386	UVM_INFO @ 405283403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	111170950364029660237977924464035439167184301114986057825022161025886709655542	386	UVM_INFO @ 486147446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	30907579191661716581369872459128112975487077602564540808741383934948574302886	386	UVM_INFO @ 415291577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	67571082971294550286271490653564821862083619740443677391010440904025593027773	386	UVM_INFO @ 441313419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	105932335372537458838367334875423222755868837254122550244035811230260580139129	386	UVM_INFO @ 428511300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	53095727140775410932302494453197993705927424345809498180950855973219696784513	406	UVM_INFO @ 1335696898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	95678114101208011236891705607231780975561319720009550228091195372612137143365	486	UVM_INFO @ 42714732726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	96893055356064146754951901196792426192878639393347656630218763205245825630412	386	UVM_INFO @ 501247032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	64050457377578301968599771057723739806144974698406612144504345824141770029577	386	UVM_INFO @ 287317805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	108790526267359730292681861309254234643645505022170659521515709444991638760776	386	UVM_INFO @ 315245791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	88476909347727781616101993547929860646774188391636180386178964309683294480888	386	UVM_INFO @ 314778094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	97084197586800297481694126420791377104476620689361628821199408600346745772475	386	UVM_INFO @ 418525917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	112069172572770634491790867788962693115881180513933707808303391844155422109673	386	UVM_INFO @ 385784656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	22584947710167222767552485342355258640653196661729508447433818528736524037968	386	UVM_INFO @ 344928288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	100237264298802218706930413904743235604319155064569186428124328995583966131591	386	UVM_INFO @ 425014519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	100406265420238488803158559205243397622570037262972312939069254247540359179519	510	UVM_INFO @ 15502405163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	115160248090519410866980046991409938828459963088386498998812492196423083358715	387	UVM_INFO @ 824169669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	102835502722267063838424162226575287945582240235706607841347915729938617858170	386	UVM_INFO @ 445090931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	9666538354154437507333314939591379463367743647157750368204608249195685376621	386	UVM_INFO @ 366017875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	109099182201394795742398048625785115103798518558117675142943063900060776689717	386	UVM_INFO @ 281556135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	11560661059242276478033766590196470078367198276149152306410690643972431526904	386	UVM_INFO @ 491433440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	95350204129812635880284087585909726664150117151047951994418922628665641087228	386	UVM_INFO @ 447963573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	98248512440464235778541882453602431201778009315283255093790386992942276796625	386	UVM_INFO @ 331371383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	39679034821153063414815132164931834222732500157791419456901201352477501785624	386	UVM_INFO @ 375588749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	109547610540790399631691980811394134215589788084989372227220709642234415974439	386	UVM_INFO @ 280430098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	3960434070885706897142856520452998033725786620496680460866803022034232992740	399	UVM_INFO @ 1152747356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	75177804336579270500018787497167688749041539253631136630722984772864539051036	399	UVM_INFO @ 6297096624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	71535742134711834348274577716347533000540810345506955085674334045400408802256	386	UVM_INFO @ 490642802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	5604797889751285933125264088010021453254059746560737860428206334956328486865	386	UVM_INFO @ 291586485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	17271629925356230661871566290454338161270188701562707330245289323260993220980	386	UVM_INFO @ 303204619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	15218048260572713979223662813257699937383963015174985537285487165897218493963	386	UVM_INFO @ 502959036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	12380785872921911131328764070436681373522033725574224173318343713005111986217	386	UVM_INFO @ 321060476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	50072892290091538307599433321827826531040055672751713324523487051095400136591	386	UVM_INFO @ 422316777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	103178932504963128235400652361972518982247581040005839889445406668535413241469	386	UVM_INFO @ 460333280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	48927298308501565647824613648004557370672217508498547942536059902615244811882	386	UVM_INFO @ 388008949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	78835421984119429955697099191938325550399424702917645652522589573217284897861	392	UVM_INFO @ 717034032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	31773729807138217868412002754106950162096138203011381956659444712668236871884	389	UVM_INFO @ 6764344156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	59349642185573328596111047153118159883280633634925289969495413363858873368418	386	UVM_INFO @ 331079570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	115026981554413758798873666597179908981654678349623869114751291336242210667858	386	UVM_INFO @ 319217468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	90127811588525130222318573116249629450453893555245506665604658858561994377146	386	UVM_INFO @ 276285557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	15891863194008674203460804704135296968485143087129420830320577317576449063560	386	UVM_INFO @ 467088307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	47933253105577470029520909823036600592165284534938401134529990067054591715507	386	UVM_INFO @ 316905183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	4651026588525249256303545227522038763630780696568896713004497397186225648679	386	UVM_INFO @ 548715858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	69776211953667867133338676143121189194202052237171135678076537421844185413651	386	UVM_INFO @ 320357084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	69759777054652946174232079384814931606522934744424097040501371482709351230356	386	UVM_INFO @ 424780418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	17895463452586403743096335816439420084464053548134149445367240733856353956140	496	UVM_INFO @ 124477520580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	72448399617462664074050520692360624659735897216290561537335766231182127158978	386	UVM_INFO @ 389697594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	111018088085509918833580807071625889891373183250258895661180003174898635792461	386	UVM_INFO @ 350429676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	101956570165364070442866807583969507336735811994023625973315706099439860741095	386	UVM_INFO @ 409255743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	103899668031331901181169614376348712111675634435133073895121154750412434412926	386	UVM_INFO @ 424708161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	73033545921142447702031200275528851197719714349172459879467321009272162806602	386	UVM_INFO @ 412208774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	61390245986430762253259406018921113545549265381318379129282310075252930873289	386	UVM_INFO @ 313692035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	44250294313754407509445130068667257910796139803735491062332819081391068197884	386	UVM_INFO @ 366174818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	18244954509288353781984028186629481189731684524408516644533835754639942140729	386	UVM_INFO @ 512575245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	18771817520465697880903601772918699995974343208020322681210495763042041328793	428	UVM_INFO @ 5412324651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	62918861330992296591108943586287615881792706266075741544191648257084629672	387	UVM_INFO @ 783145789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	34859784335507277820052416649798945464597264387754470966003522145068756233132	386	UVM_INFO @ 306373496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	108468595236388151628947779927202533149034023365834480175314847670541740521317	386	UVM_INFO @ 461538908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	87697638531107679281564936016870809403538710435246837367860226912901684301143	386	UVM_INFO @ 429383260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	74562075590924729784129676178289034434864681694480843224136476098507130355023	386	UVM_INFO @ 499508810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	78715872571074331807059268726518602037073418928337398613258574288800403983255	386	UVM_INFO @ 500159659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	78118597128001523286044713501289617476150489610018448379343355338062223768688	386	UVM_INFO @ 355067316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	43168983324311543492200463944364518289220476754493756112673691554254131036538	386	UVM_INFO @ 510836819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	28138811285314999295222594226386718257286692529379066181799694793996113634105	386	UVM_INFO @ 306137730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	7729115243659726080067878535294934462809415155370701129026296781131419151374	406	UVM_INFO @ 927915049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	20466746613812490676495617361518026545305026336988037035952132756522018018690	387	UVM_INFO @ 932704706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---