| V1 |
|
100.00% |
| V2 |
|
97.25% |
| V2S |
|
91.12% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 3.000s | 159.215us | 1 | 1 | 100.00 | |
| smoke | 10 | 10 | 100.00 | |||
| aes_smoke | 4.000s | 170.021us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 8.000s | 88.472us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| aes_csr_rw | 2.000s | 86.998us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 14.000s | 400.699us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 14.000s | 153.505us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 2.000s | 88.278us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| aes_csr_rw | 2.000s | 86.998us | 5 | 5 | 100.00 | |
| aes_csr_aliasing | 14.000s | 153.505us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 70 | 70 | 100.00 | |||
| aes_smoke | 4.000s | 170.021us | 10 | 10 | 100.00 | |
| aes_config_error | 34.000s | 96.006us | 50 | 50 | 100.00 | |
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| key_length | 70 | 70 | 100.00 | |||
| aes_smoke | 4.000s | 170.021us | 10 | 10 | 100.00 | |
| aes_config_error | 34.000s | 96.006us | 50 | 50 | 100.00 | |
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| back2back | 35 | 35 | 100.00 | |||
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| aes_b2b | 41.000s | 369.637us | 25 | 25 | 100.00 | |
| backpressure | 10 | 10 | 100.00 | |||
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| multi_message | 95 | 95 | 100.00 | |||
| aes_smoke | 4.000s | 170.021us | 10 | 10 | 100.00 | |
| aes_config_error | 34.000s | 96.006us | 50 | 50 | 100.00 | |
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| aes_alert_reset | 32.000s | 70.781us | 25 | 25 | 100.00 | |
| failure_test | 85 | 85 | 100.00 | |||
| aes_man_cfg_err | 3.000s | 65.792us | 10 | 10 | 100.00 | |
| aes_config_error | 34.000s | 96.006us | 50 | 50 | 100.00 | |
| aes_alert_reset | 32.000s | 70.781us | 25 | 25 | 100.00 | |
| trigger_clear_test | 10 | 10 | 100.00 | |||
| aes_clear | 34.000s | 201.864us | 10 | 10 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 11.000s | 1557.112us | 1 | 1 | 100.00 | |
| reset_recovery | 25 | 25 | 100.00 | |||
| aes_alert_reset | 32.000s | 70.781us | 25 | 25 | 100.00 | |
| stress | 10 | 10 | 100.00 | |||
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| sideload | 20 | 20 | 100.00 | |||
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| aes_sideload | 7.000s | 931.714us | 10 | 10 | 100.00 | |
| deinitialization | 10 | 10 | 100.00 | |||
| aes_deinit | 5.000s | 150.441us | 10 | 10 | 100.00 | |
| stress_all | 4 | 10 | 40.00 | |||
| aes_stress_all | 64.000s | 4649.520us | 4 | 10 | 40.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| aes_alert_test | 32.000s | 53.267us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| aes_tl_errors | 4.000s | 611.493us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| aes_tl_errors | 4.000s | 611.493us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| aes_csr_hw_reset | 8.000s | 88.472us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 86.998us | 5 | 5 | 100.00 | |
| aes_csr_aliasing | 14.000s | 153.505us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 152.358us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| aes_csr_hw_reset | 8.000s | 88.472us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 86.998us | 5 | 5 | 100.00 | |
| aes_csr_aliasing | 14.000s | 153.505us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 152.358us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 8 | 10 | 80.00 | |||
| aes_reseed | 8.000s | 424.412us | 8 | 10 | 80.00 | |
| fault_inject | 587 | 660 | 88.94 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 82.005us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 82.005us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 82.005us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 82.005us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 19 | 20 | 95.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 7.000s | 10053.491us | 19 | 20 | 95.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| aes_sec_cm | 10.000s | 1906.757us | 5 | 5 | 100.00 | |
| aes_tl_intg_err | 4.000s | 530.239us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| aes_tl_intg_err | 4.000s | 530.239us | 25 | 25 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 25 | 25 | 100.00 | |||
| aes_alert_reset | 32.000s | 70.781us | 25 | 25 | 100.00 | |
| sec_cm_main_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 82.005us | 20 | 20 | 100.00 | |
| sec_cm_gcm_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 82.005us | 20 | 20 | 100.00 | |
| sec_cm_main_config_sparse | 134 | 145 | 92.41 | |||
| aes_smoke | 4.000s | 170.021us | 10 | 10 | 100.00 | |
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| aes_alert_reset | 32.000s | 70.781us | 25 | 25 | 100.00 | |
| aes_core_fi | 77.000s | 10020.396us | 89 | 100 | 89.00 | |
| sec_cm_gcm_config_sparse | 149 | 160 | 93.12 | |||
| aes_config_error | 34.000s | 96.006us | 50 | 50 | 100.00 | |
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| aes_core_fi | 77.000s | 10020.396us | 89 | 100 | 89.00 | |
| sec_cm_aux_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 82.005us | 20 | 20 | 100.00 | |
| sec_cm_aux_config_regwen | 20 | 20 | 100.00 | |||
| aes_readability | 3.000s | 70.952us | 10 | 10 | 100.00 | |
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| sec_cm_key_sideload | 20 | 20 | 100.00 | |||
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| aes_sideload | 7.000s | 931.714us | 10 | 10 | 100.00 | |
| sec_cm_key_sw_unreadable | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 70.952us | 10 | 10 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 70.952us | 10 | 10 | 100.00 | |
| sec_cm_key_sec_wipe | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 70.952us | 10 | 10 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 70.952us | 10 | 10 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 70.952us | 10 | 10 | 100.00 | |
| sec_cm_data_reg_key_sca | 10 | 10 | 100.00 | |||
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| sec_cm_key_masking | 10 | 10 | 100.00 | |||
| aes_stress | 6.000s | 215.844us | 10 | 10 | 100.00 | |
| sec_cm_main_fsm_sparse | 0 | 10 | 0.00 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| sec_cm_main_fsm_redun | 612 | 685 | 89.34 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| aes_ctr_fi | 4.000s | 55.913us | 25 | 25 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 0 | 10 | 0.00 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| sec_cm_cipher_fsm_redun | 587 | 660 | 88.94 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| sec_cm_cipher_ctr_redun | 319 | 350 | 91.14 | |||
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| sec_cm_ctr_fsm_sparse | 0 | 10 | 0.00 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| sec_cm_ctr_fsm_redun | 293 | 335 | 87.46 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_ctr_fi | 4.000s | 55.913us | 25 | 25 | 100.00 | |
| sec_cm_ghash_fsm_sparse | 0 | 10 | 0.00 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| sec_cm_ctrl_sparse | 612 | 685 | 89.34 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| aes_ctr_fi | 4.000s | 55.913us | 25 | 25 | 100.00 | |
| sec_cm_main_fsm_global_esc | 25 | 25 | 100.00 | |||
| aes_alert_reset | 32.000s | 70.781us | 25 | 25 | 100.00 | |
| sec_cm_main_fsm_local_esc | 612 | 685 | 89.34 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| aes_ctr_fi | 4.000s | 55.913us | 25 | 25 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 612 | 685 | 89.34 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| aes_ctr_fi | 4.000s | 55.913us | 25 | 25 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 293 | 335 | 87.46 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_ctr_fi | 4.000s | 55.913us | 25 | 25 | 100.00 | |
| sec_cm_ghash_fsm_local_esc | 0 | 10 | 0.00 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| sec_cm_data_reg_local_esc | 587 | 660 | 88.94 | |||
| aes_fi | 10.000s | 379.955us | 0 | 10 | 0.00 | |
| aes_control_fi | 62.041s | 0.000us | 268 | 300 | 89.33 | |
| aes_cipher_fi | 61.000s | 0.000us | 319 | 350 | 91.14 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| aes_stress_all_with_rand_reset | 54.000s | 5140.545us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! | 28 test runs | |||
| aes_cipher_fi | 112865140762480921089705840730082480430223818791864679295095434121122620538384 | 142 |
UVM_INFO @ 10004703719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 43459779913017836817176027265309850273268696675852522004187903111098312782342 | 143 |
UVM_INFO @ 10006332823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 41824988275643312545937114940602553110557687413400505343390894210608869866876 | 148 |
UVM_INFO @ 10007426243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 108620666109505342391512941397589544525304538598610195571889835639154089372823 | 150 |
UVM_INFO @ 10112135213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 93666981656142979694032567471617472640728132021369010772574469392997515471981 | 140 |
UVM_INFO @ 10071132983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 8146323749241114981944175542944087213392354373970400408179888743536377372855 | 148 |
UVM_INFO @ 10017461527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 114561288698807802690076137025429776326493599074354792556891264945122959173520 | 146 |
UVM_INFO @ 10008182544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 69237815428646276791419575805497149437368268120891585094247400293710898277786 | 142 |
UVM_INFO @ 10018452939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 22867554029285621594917949210211876456382039345347373577437033443041037783420 | 140 |
UVM_INFO @ 10014541863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 115289534980458014273686110751663673768234905608807980562719350299047002938302 | 145 |
UVM_INFO @ 10278694140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 34035219501371948275878281835336052739044943962725188351868486970869340524339 | 139 |
UVM_INFO @ 10017763439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 83785053062740505391270620095767097194710051859956686619688011628965519355220 | 150 |
UVM_INFO @ 10022016137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 106277850006659058453955638493721120627784094747749565626658939324074881101700 | 143 |
UVM_INFO @ 10009836897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 63587353846029353263482143493402790126970055247788229914383477538666728656789 | 142 |
UVM_INFO @ 10013921333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 10972304325525337105021821917496970192477070703604177334218467619395850214995 | 144 |
UVM_INFO @ 10006282253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 78765710792842645351869630347158723186819844563365088290760850653255594881502 | 140 |
UVM_INFO @ 10012620142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 81316787185434575203581422182429413595592198625812883763667895541197313723484 | 141 |
UVM_INFO @ 10016951813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 4751238985785376202602667115694619643959560552313595373210254324997026338659 | 148 |
UVM_INFO @ 10008887527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 113392463237123080773641725490390484154748929675876895793957623951206227832020 | 140 |
UVM_INFO @ 10016707854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 96910917183559922192846897459644928478343060344781534886103480993142095473664 | 144 |
UVM_INFO @ 10015108515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 89472669211588174305947699452120589162026164195627034274198884064845530213626 | 141 |
UVM_INFO @ 10099216107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 60399147792838897228123046440619393686074240482517549575819861015279870939748 | 145 |
UVM_INFO @ 10074394866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 29029096088613305728362823689606401663515130820601167760395130349936081814127 | 142 |
UVM_INFO @ 10006682508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 113340746036535418899449982451123572236751039269722286922958141938391063624984 | 149 |
UVM_INFO @ 10016910342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 13605729300982575827373037435593276348481258923981431108954714223622255035022 | 147 |
UVM_INFO @ 10039652271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 20340202056557194883073776681712909001197072090457230421643366587749978649886 | 148 |
UVM_INFO @ 10020451550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 97567446536741616034540929739809172084756112442633036216764288984385310626675 | 140 |
UVM_INFO @ 10145479399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 4347273740594263568817835263736872789580265144018501260609794832765834038894 | 143 |
UVM_INFO @ 10010971631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! | 21 test runs | |||
| aes_control_fi | 40118745782876595229945275270674981177111595574135794296524494112943785553758 | 143 |
UVM_INFO @ 10029945368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 25094158315936845227091396030031109546682569057974528403520048271933695161655 | 150 |
UVM_INFO @ 10021337429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 60097705166368852312802300453153471985297017363983746111197951373362369101213 | 150 |
UVM_INFO @ 10010556354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 105634654317794244938072942882125886878216432718606303314033471909257062439197 | 153 |
UVM_INFO @ 10106618009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 85533058153896489163672341259308272146436662232048009560737177729192494156306 | 143 |
UVM_INFO @ 10063876236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 80922692279838627944119711069126994053618710425772650715552942726691334548567 | 141 |
UVM_INFO @ 10017975471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 35110610614913765467470322567356686062149098554020867031778180779748643143653 | 149 |
UVM_INFO @ 10008012539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 24695793507402686320220696874196786486946377483086102912733010927140438933413 | 151 |
UVM_INFO @ 10025500842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 26263355033897215835093832092322038368894453854214989750944416259855547727214 | 138 |
UVM_INFO @ 10032309219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 51358662406626401301203680747839531091092539115736665819970813848499319991130 | 142 |
UVM_INFO @ 10035846850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 21009821490114358279219638901412652808485943809874517169914341477771932767143 | 153 |
UVM_INFO @ 10010143277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 64125747064127454983628109023860000021011415103369393435233188789331645753568 | 151 |
UVM_INFO @ 10015235873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 91600949227855638690218145713158691966463423677186291561466681865694653811296 | 146 |
UVM_INFO @ 10030953701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 77925297533779635186117842694918616189045357416766431407123632195925616974822 | 144 |
UVM_INFO @ 10066357967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 19404038883218128168355419349218439998150571178666111413642340990225178942686 | 147 |
UVM_INFO @ 10010664581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 102379576522692942376306908212841188501835872946305599106885327665224429632480 | 147 |
UVM_INFO @ 10179392471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 59051422036934104291898250872536255074519286485960144843068229445681031093264 | 143 |
UVM_INFO @ 10009623609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 16672192867811132775604256513253843507631904760573567820609159107103168268342 | 138 |
UVM_INFO @ 10007237944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 32865798248152639055219326841209719022573779645445170616147887009498212337234 | 143 |
UVM_INFO @ 10056968104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 82663429530332495077439566434342857036739791946297595465619848166934618725603 | 147 |
UVM_INFO @ 10007059733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 79920110307426822602377848124541566903316920551671178059666210984439986829181 | 152 |
UVM_INFO @ 10027886512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 14 test runs | |||
| aes_cipher_fi | 16605544645891585981118577732406726474777609803406805369778820154308252893900 | None | ||
| aes_control_fi | 87433735655226766517961807709508473212867502440908369831517013116334200910077 | None | ||
| aes_control_fi | 99644750852635306958872418738458316245131642878152808757276614314189111039413 | None | ||
| aes_control_fi | 100848930326504062680289179637670123103572662344072674867726247877352721383383 | None | ||
| aes_cipher_fi | 35403196237727828855608549734247453910354798718021076439031898042113413132729 | None | ||
| aes_control_fi | 96156273482355663042291847342899454889796744796420590613889251499243368184029 | None | ||
| aes_control_fi | 84870813359592822108425027372072170035845207373279803485329729560015818515961 | None | ||
| aes_control_fi | 112979491771228971845498607624172171773706910035705314409574806024099396741809 | None | ||
| aes_control_fi | 95652866692208146494439999893426839313955825560118037722449307018713392527814 | None | ||
| aes_control_fi | 8994534827335774762210701285142975735606220765691186812269607505522287031770 | None | ||
| aes_cipher_fi | 10349987421946392006522207186691297430189775441232148308057455165221175618280 | None | ||
| aes_control_fi | 77086394289590873505390361314499536577347921670583850976464524330054671977990 | None | ||
| aes_control_fi | 83606523855077472966859355541164707590188637073085074388388789112078983802449 | None | ||
| aes_control_fi | 114429831272614646538455749175232300300088538990459444483179329116734933930195 | None | ||
| UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] | 11 test runs | |||
| aes_fi | 23038321797875403739664231691239148874031716132904683806844945795738116394871 | 18601 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
|
|
| aes_fi | 68489699810551486746056821847453613102191037151701625960397052469463284177250 | 8947 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
|
|
| aes_fi | 55586278368444602220315330506657715005235722421414004805119649255055673377447 | 28887 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
|
|
| aes_fi | 68687287772815566447951955431532933122912476986615555659858140677491081993771 | 8119 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
|
|
| aes_fi | 1808736031897256582711356368934961261059173425972098492746802608607540274733 | 6818 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
|
|
| aes_fi | 100504340858991453049285694799598024320898059482812241810670197047035383870485 | 15522 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
|
|
| aes_fi | 54787963742734163710923393206587968048952152879173495833104262964970426133972 | 4707 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
|
|
| aes_fi | 115426958920933068396362093276107848150858486423617650175367618141952309139109 | 15717 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
|
|
| aes_fi | 3410487055273471950653671805204665217019158121983347521670393310852569683361 | 14472 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
|
|
| aes_stress_all | 97290507723692673504589215797238592417061098605033885952661028688867024096204 | 127133 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 2
----| Seen: 1
----| Expected corrupted: 0
|
|
| aes_fi | 104625010911039134149461753430796093779362448656149503834898412425254093199101 | 8639 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
|
|
| UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! | 11 test runs | |||
| aes_core_fi | 96935279562644340621354936835902911228004835674277827890825525406308580132960 | 139 |
UVM_INFO @ 10004634597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 871372423852489673334444960488593411975545592779119551228681665820440545397 | 145 |
UVM_INFO @ 10020396498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 83622993145606026263124606756365069665431322269213414838243257178112112835192 | 148 |
UVM_INFO @ 10034067175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 35568197374002755610250455225007679139901137091255647496085062298016523584244 | 145 |
UVM_INFO @ 10077321043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 84314011605488510689991716123758421823460700882906344489301584549784976194563 | 145 |
UVM_INFO @ 10017962691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 31024725772596309696435803313051070488161585390648186271195715343643103589432 | 146 |
UVM_INFO @ 10010944727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 44737841882680542035488850548274554247185923962214859666545620362249046968735 | 144 |
UVM_INFO @ 10059465543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 28453861814983636434148106417924397225107928238791138324198957014461940281423 | 140 |
UVM_INFO @ 10026164261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 43790500763679084028479290752736888914796088696775851184829506651072370223080 | 140 |
UVM_INFO @ 10016764414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 39643562459242501051503319287968729100106296198726305205358941234444886114381 | 148 |
UVM_INFO @ 10014999672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 45172677833720560334780589589543224345058867836781027608339061470596871406304 | 146 |
UVM_INFO @ 10006917542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 10 test runs | |||
| aes_stress_all | 106247243213030914310081489958525089353277997779859595825690584525811227453976 | 69077 |
UVM_INFO @ 5807584725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 97423038388438037010202577998513851039626724131624857636887825689118643130367 | 240 |
UVM_INFO @ 585842498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_reseed | 6825332848458430092814947239126869825979322232718541353202223350710378371416 | 2633 |
UVM_INFO @ 24772529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all | 28803329953239659540423115166794461558686980995235103618008215791812026613716 | 22565 |
UVM_INFO @ 1514781381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_reseed | 47701197689415058012451369400129399763117363260202041167562420641594583974887 | 4962 |
UVM_INFO @ 18343307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 3440545507823967521936229450300525661010416075178158747106310341731138682129 | 256 |
UVM_INFO @ 185801733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all | 87836483193004304041563323378037498615235588047825139537409243792069685644873 | 34892 |
UVM_INFO @ 932334517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 93058560915081517279674682496477360606777896216773370748217207069212204702435 | 210 |
UVM_INFO @ 110407753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 9112576947887517024308770227944225251175514044086540065493079731882841397219 | 974 |
UVM_INFO @ 5140544973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 109987969120255395615187580898394539662579309211010042704928142304194560976177 | 354 |
UVM_INFO @ 551387580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:1082) virtual_sequencer [aes_stress_vseq] | 2 test runs | |||
| aes_stress_all_with_rand_reset | 31051138141967867119082168898521921465981919405291881692741900203519234148878 | 165 |
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0
|
|
| aes_stress_all_with_rand_reset | 33072951295032407274840745789389536821738370525226406341586503339242091625912 | 149 |
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0
|
|
| UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * | 1 test run | |||
| aes_stress_all | 108185373916529252844832933829355978929427944537337563138462081677859627340163 | 91181 |
TEST FAILED MESSAGES DID NOT MATCH
0 63 77 77 0
1 00 8f 8f 0
|
|
| UVM_FATAL (aes_base_vseq.sv:104) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | 1 test run | |||
| aes_stress_all_with_rand_reset | 489061831651409552601225841795734690412151181519949312778821524633986772564 | 111 |
UVM_INFO @ 9939245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:87) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | 1 test run | |||
| aes_stress_all_with_rand_reset | 64141441274298554914472547128795649440343454415946975279686333424031980471264 | 111 |
UVM_INFO @ 60387910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1113): Assertion AesModeValid has failed | 1 test run | |||
| aes_stress_all | 42818943976845451985541378907049621027422544414063758781190418087483682832301 | 15545 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 2222064779 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 2222064779 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 2222064779 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 2222064779 ps: (aes_core.sv:1113) [ASSERT FAILED] AesModeValid
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) | 1 test run | |||
| aes_stress_all_with_rand_reset | 62435501086057114511291251422368579797101779436235702989763303780024456788580 | 137 |
UVM_INFO @ 7400233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout | 1 test run | |||
| aes_shadow_reg_errors_with_csr_rw | 46053051924890888731093519912047402791830819875044626571734755495508406283108 | 106 |
UVM_INFO @ 10053490688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|