| V1 |
|
100.00% |
| V2 |
|
89.35% |
| V2S |
|
99.02% |
| V3 |
|
10.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 68.610s | 4262.266us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 10.640s | 392.350us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 12.020s | 158.368us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 189.700s | 10505.178us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 126.660s | 3750.409us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 14.620s | 355.231us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 12.020s | 158.368us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 126.660s | 3750.409us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 318.400s | 6204.529us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 78.080s | 5326.174us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2745.400s | 278481.328us | 25 | 25 | 100.00 | |
| sig_int_fail | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 74.250s | 2686.741us | 49 | 50 | 98.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 68.610s | 4262.266us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 48.720s | 1578.009us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 78.840s | 1417.895us | 50 | 50 | 100.00 | |
| ping_timeout | 20 | 50 | 40.00 | |||
| alert_handler_ping_timeout | 454.930s | 25579.918us | 20 | 50 | 40.00 | |
| lpg | 98 | 100 | 98.00 | |||
| alert_handler_lpg | 3011.140s | 776014.684us | 49 | 50 | 98.00 | |
| alert_handler_lpg_stub_clk | 2660.890s | 241906.801us | 49 | 50 | 98.00 | |
| stress_all | 48 | 50 | 96.00 | |||
| alert_handler_stress_all | 3953.700s | 84805.339us | 48 | 50 | 96.00 | |
| alert_handler_entropy_stress_test | 1 | 20 | 5.00 | |||
| alert_handler_entropy_stress | 22.630s | 502.579us | 1 | 20 | 5.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 4.820s | 248.388us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.170s | 28.177us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 26.640s | 322.819us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 26.640s | 322.819us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 10.640s | 392.350us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 12.020s | 158.368us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 126.660s | 3750.409us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 42.730s | 2009.715us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 10.640s | 392.350us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 12.020s | 158.368us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 126.660s | 3750.409us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 42.730s | 2009.715us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 357.610s | 13085.599us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 357.610s | 13085.599us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 357.610s | 13085.599us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 357.610s | 13085.599us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1141.820s | 307422.601us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 95.830s | 2298.029us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 95.830s | 2298.029us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 357.610s | 13085.599us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 68.610s | 4262.266us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 68.610s | 4262.266us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 68.610s | 4262.266us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 68.610s | 4262.266us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 74.250s | 2686.741us | 49 | 50 | 98.00 | |
| sec_cm_lpg_intersig_mubi | 49 | 50 | 98.00 | |||
| alert_handler_lpg | 3011.140s | 776014.684us | 49 | 50 | 98.00 | |
| sec_cm_esc_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 74.250s | 2686.741us | 49 | 50 | 98.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2745.400s | 278481.328us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2745.400s | 278481.328us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.580s | 1262.877us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 10 | 10.00 | |||
| alert_handler_stress_all_with_rand_reset | 308.390s | 3990.127us | 1 | 10 | 10.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 25 test runs | |||
| alert_handler_ping_timeout | 16780089451542369556991409714518356599909771921929938860719596994197715179897 | 117 |
UVM_INFO @ 14116657596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 66216030648894533345063035722763422259135944054009800801474615959740422620524 | 108 |
UVM_INFO @ 4906400392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 17391549380095953456404921510058350249286826498365622804426625621202165930239 | 94 |
UVM_INFO @ 26449102933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80576586859286488618089707201137647742195380627112055385186995305200116668981 | 111 |
UVM_INFO @ 7950872577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 100918622442479837795508386415604392143297608655245049706379690646691658601110 | 105 |
UVM_INFO @ 21012403123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 36158331839974252091620748118366623801333369965676038229959575670866846804856 | 99 |
UVM_INFO @ 3030414210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80867140184640416351024537683674544695069961564268792143690909405085309210494 | 114 |
UVM_INFO @ 12134800330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 105447737210242391097427570553042226506861619643717306901320974243659219508344 | 87 |
UVM_INFO @ 6131620064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 55440182514922994822651211708744115403216319383797519780135803406485331051540 | 108 |
UVM_INFO @ 4116014644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70908366382027315427814350719848562164186493752306626126366075927601156128831 | 126 |
UVM_INFO @ 19412978826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 100199258592926356922818285290533169581552086530323791816925377477358637603831 | 118 |
UVM_INFO @ 107244047478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78185024057556302155573975367470843766783904030936727275920422512114600078602 | 93 |
UVM_INFO @ 21341483292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 105011815368336632282278357931581587130664394022441268923174399299900766120376 | 93 |
UVM_INFO @ 1498543917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53639488768823208839310441625580739628105022863600281131023076469796260977229 | 90 |
UVM_INFO @ 4899422169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 73729249957496422307071001291436721704221295798907087691783326236053618527969 | 87 |
UVM_INFO @ 3095659390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 49712380180666835177337512724435843148349730677467874219219993072860269765166 | 127 |
UVM_INFO @ 10433595996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 86378996317943711698493092094721550882325181169283580312760535419321374520174 | 91 |
UVM_INFO @ 1822935724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 8318612957949707919992701860166176847109207748362069943060715268307788026450 | 114 |
UVM_INFO @ 8104583314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 5850426235665128712511418864419489147947310157144600745161491259234098566423 | 117 |
UVM_INFO @ 5943923423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 89130217577427500944648625129091844728057966122469138202629565699373655296969 | 90 |
UVM_INFO @ 8927929029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 65065161787236241923302852858045888046864288740167136489359740355834593513029 | 87 |
UVM_INFO @ 11230275959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all | 83819887324105545504837602399266146308257972332122282436562047120503473362897 | 80 |
UVM_INFO @ 35259449967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 111056556323309319289973761452443677522198636101568091550850512688189978382951 | 90 |
UVM_INFO @ 3518752259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 113771893596680161946056722180834472205732909391250527125498785644812698752830 | 126 |
UVM_INFO @ 33363528655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 97988645254147990713908649011703465710182568361606471557335593826283370686766 | 126 |
UVM_INFO @ 18384303700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 19 test runs | |||
| alert_handler_entropy_stress | 64766700851804835165481739609991679324007893166754050209461071806460301286507 | 198 |
UVM_INFO @ 480547615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 49628183344288232052892985194528771244127503552390980703410961166394241994149 | 184 |
UVM_INFO @ 116843348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 18588969712723071439360161744444358242117394731923486418410297445253483141846 | 184 |
UVM_INFO @ 303033328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 55291515549031229319351039247074987561335335141437858598069594954401266665892 | 204 |
UVM_INFO @ 126941415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 74836684774464106349795971427667107721128962186789739955375977373515822914387 | 194 |
UVM_INFO @ 484025883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 46871986427764811131374357975257141659784020342640506050843833325417329452353 | 186 |
UVM_INFO @ 954174854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 90649455491040718323599810431279996861975112200435551344381007195462137426089 | 176 |
UVM_INFO @ 786980866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 110097546806869349004247002158314663850724301894916173752912704058573615853337 | 138 |
UVM_INFO @ 266547930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 111210850792262740281834720265541768332142151831307898480934775281477802036677 | 202 |
UVM_INFO @ 1183412744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 104537639958041974270880007656923179369178006404824124605523125020811720023777 | 160 |
UVM_INFO @ 305253977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 17695085055532660101618597991609991549813965620341693718140451831186318410268 | 166 |
UVM_INFO @ 92337726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 13228748051399364640578018606754023555321681886645678672873963033889201132207 | 170 |
UVM_INFO @ 761429003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 4432101839778954464399647039917017892442129564002215565215017979187952785032 | 154 |
UVM_INFO @ 67299646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 66636313572756545848889737981433382773555218375152121975433421917211867697855 | 162 |
UVM_INFO @ 335445069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 66910515798060190573878143383340505314049127778617117820534261412980103173260 | 190 |
UVM_INFO @ 161269826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 114616715517758176276329259511548241447204010180908444561226621270512963263391 | 170 |
UVM_INFO @ 502579012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 17536286621472813824197112832923318880315564120500438516997363648816588088104 | 122 |
UVM_INFO @ 57404258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 74406511340357758589300926957872505702873832912293613164091651820432659797290 | 184 |
UVM_INFO @ 486129101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 79115688848090471908878908674346699450706016367449247799529325655045607360178 | 196 |
UVM_INFO @ 84073778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 8 test runs | |||
| alert_handler_stress_all_with_rand_reset | 67171979339311368815481242573181326204781349141281935951469761431941551660044 | 104 |
UVM_INFO @ 1536096100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 7913065316729654803637085600084635567330675957222340177341604441636139504516 | 119 |
UVM_INFO @ 13972737538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 106244987769903987215880832097345769416262198362348754190919513096306058197082 | 137 |
UVM_INFO @ 6115303837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 48355265576728765102158760716335422792329558285905280423800136820799164901659 | 156 |
UVM_INFO @ 7062308263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 10830146869944380568982484822172663591416964989292850703609342995389577435426 | 168 |
UVM_INFO @ 16682421506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 45700984712888183535353514308310370552220551549307441219468578100542951213622 | 82 |
UVM_INFO @ 231217393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 7155888322659038933242384512842159682950255922621233833134873359286596075969 | 105 |
UVM_INFO @ 2364903643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 65466324083489674832054073203809380350155922955701781998986914152298793022537 | 126 |
UVM_INFO @ 2833239107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 5 test runs | |||
| alert_handler_ping_timeout | 32709773139824879544620820393005431781449458778849087168086616035445595866675 | 80 |
UVM_INFO @ 619921398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 112847496301159226034019793062243375505058163074222536244330674741503129830454 | 83 |
UVM_INFO @ 5630945809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 15891497312241725048329166318083856295585681095795724441626568889351102506577 | 80 |
UVM_INFO @ 692063748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 48741535362340053601076276299895819368387691319616010390554638764835661212103 | 80 |
UVM_INFO @ 54816768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 51123390053616671915322593379978647472044109666750190131260164709620387070812 | 80 |
UVM_INFO @ 1137278747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1199) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. | 1 test run | |||
| alert_handler_stress_all_with_rand_reset | 25589494612645748285170685285403649688175151530604282342587580504333492581490 | 102 |
UVM_INFO @ 813925399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:343) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) | 1 test run | |||
| alert_handler_sig_int_fail | 87459815437761020337905814732774130345130658301384328397411961112214610422102 | 82 |
UVM_INFO @ 191415956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscPingFail) | 1 test run | |||
| alert_handler_ping_timeout | 7767188279782183108170767595936219205829386833582853890985909099170484509800 | 94 |
UVM_INFO @ 2245477065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt | 1 test run | |||
| alert_handler_lpg_stub_clk | 79575359326584466787623929325680665032044995522872651030063311103712891312967 | 80 |
UVM_INFO @ 118448044780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* | 1 test run | |||
| alert_handler_lpg | 48965221782711450109403993688197435399477062859280759926007863838531060643260 | 80 |
UVM_INFO @ 12814197016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state | 1 test run | |||
| alert_handler_stress_all | 79021005598057837957122513076145076016576961457147196504200977809532055782952 | 186 |
UVM_INFO @ 131449209488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|