Simulation Results: clkmgr

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.29 %
  • code
  • 98.85 %
  • assert
  • 96.19 %
  • func
  • 87.82 %
  • line
  • 99.28 %
  • branch
  • 99.06 %
  • cond
  • 95.93 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
78.62%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.410s 82.561us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.140s 20.698us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.570s 149.394us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.570s 412.806us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.430s 134.932us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.760s 74.938us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.570s 149.394us 5 5 100.00
clkmgr_csr_aliasing 2.430s 134.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.270s 80.410us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.650s 143.756us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.480s 99.432us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.180s 46.439us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.410s 82.561us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 17.680s 2002.385us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 17.350s 2178.480us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 17.680s 2002.385us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 50.160s 7132.416us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.300s 69.732us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 6.330s 743.857us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 6.330s 743.857us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.140s 20.698us 1 1 100.00
clkmgr_csr_rw 1.570s 149.394us 5 5 100.00
clkmgr_csr_aliasing 2.430s 134.932us 1 1 100.00
clkmgr_same_csr_outstanding 2.060s 111.045us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.140s 20.698us 1 1 100.00
clkmgr_csr_rw 1.570s 149.394us 5 5 100.00
clkmgr_csr_aliasing 2.430s 134.932us 1 1 100.00
clkmgr_same_csr_outstanding 2.060s 111.045us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 14 30 46.67
clkmgr_sec_cm 61.190s 10005.712us 1 5 20.00
clkmgr_tl_intg_err 55.090s 10005.859us 13 25 52.00
shadow_reg_update_error 13 20 65.00
clkmgr_shadow_reg_errors 1077.440s 200000.000us 13 20 65.00
shadow_reg_read_clear_staged_value 13 20 65.00
clkmgr_shadow_reg_errors 1077.440s 200000.000us 13 20 65.00
shadow_reg_storage_error 13 20 65.00
clkmgr_shadow_reg_errors 1077.440s 200000.000us 13 20 65.00
shadowed_reset_glitch 13 20 65.00
clkmgr_shadow_reg_errors 1077.440s 200000.000us 13 20 65.00
shadow_reg_update_error_with_csr_rw 12 20 60.00
clkmgr_shadow_reg_errors_with_csr_rw 935.230s 200000.000us 12 20 60.00
sec_cm_bus_integrity 13 25 52.00
clkmgr_tl_intg_err 55.090s 10005.859us 13 25 52.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 17.680s 2002.385us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 17.350s 2178.480us 10 10 100.00
sec_cm_meas_config_shadow 13 20 65.00
clkmgr_shadow_reg_errors 1077.440s 200000.000us 13 20 65.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.570s 85.067us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.280s 49.130us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.350s 73.927us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_clk_handshake_intersig_mubi 1.740s 166.424us 10 10 100.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.730s 190.578us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.570s 149.394us 5 5 100.00
sec_cm_idle_ctr_redun 1 5 20.00
clkmgr_sec_cm 61.190s 10005.712us 1 5 20.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.570s 149.394us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.570s 149.394us 5 5 100.00
prim_count_check 1 5 20.00
clkmgr_sec_cm 61.190s 10005.712us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 7.600s 1094.429us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 203.470s 68750.000us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 14 test runs
clkmgr_tl_intg_err 102716659996426313624576401964498574012308767089293294939697876465265411696606 82
UVM_INFO @ 10005858901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 34870147575433345219085304165910644887782478234475640947457157106112761534562 81
UVM_INFO @ 10005712333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 96799585737969566523368332516066023380641160787231696112774541734289981577104 180
UVM_INFO @ 10215735030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 19811861203807821379213260011553153650142932401279738749888846571284653263458 150
UVM_INFO @ 10133359703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 47302088589016696152503077970542363209601960593389838092261955711524143396804 145
UVM_INFO @ 10168218640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 27564039667260192940032591927569075096107994600373337063676209383360330334704 125
UVM_INFO @ 10162532334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 764741751454688452727468215542088551390889345966038489559333412779690761748 96
UVM_INFO @ 10027798593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 85503482820696019347483177924966980678307042263727381111363614993469842114944 131
UVM_INFO @ 10129647066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 14949406490293641863904434122157364049618997818812015259589227354030442369313 115
UVM_INFO @ 10076958045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 29579356889004353705431698571511275590920333352878279388008940600577987343744 207
UVM_INFO @ 10852663399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 109274899770646242183935464470828531458736851126616503051932294726527898715334 86
UVM_INFO @ 10023932983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 14811393974174496139262685407694216161915686618115307057932037880316173523511 178
UVM_INFO @ 10375058961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 2248740773858053592894955780227116754295651202439423576306649007150394002859 160
UVM_INFO @ 10266796755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 115173649536325106192841822360774011470648160669137230635174428634831619739813 105
UVM_INFO @ 10041631636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 9 test runs
clkmgr_shadow_reg_errors 38795991637799237129757067279027186785578275877758294690319476945496793155023 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 113122012264560988789928082503182063071045992683407871107331680178383577865756 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 45342987396504813736874186197546182257147638553788214982521795454318317577550 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 96006288638420954112910720349607586982340080181691355641879467839176724309511 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 33451572887858390582340057382211201201480889907659994024156408032346603712930 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 9495814119942082343403953519328482649853767316213561346452942755124332326362 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 4410720102323632080895861800813106023507590759384925567034694509232036069368 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 49280610930594593300906444851454371055346687249755573434903396805871268281327 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 81529568835364806092976121365991560540665434701826555668915085352458246635631 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 107664359790678806522888353378764125727139275270201056384405032875377685493616 75
UVM_INFO @ 24012318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 108400594416363889357524551556189638089553274236673508912973940807966805112421 75
UVM_INFO @ 104193831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 11092981242134299442397221620086034417596397542597103488746956387247394833914 76
UVM_INFO @ 56406201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 114222460856989650409355692810135527559636338913718686622945279111389637245202 75
UVM_INFO @ 3973266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 2 test runs
clkmgr_sec_cm 92915184166576985807011069894862797761673017816301777868500273049615333932308 89
UVM_INFO @ 20850891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 905310864799585348487190472034528300719889134800526239228532920451585420667 80
UVM_INFO @ 3736299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 54178578849210238209647905248818895095330232306647550109377438559185211337936 75
UVM_INFO @ 25117677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 39499706085763016511670799207454923190845351209933641694921158331023084784626 75
UVM_INFO @ 96543177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---