Simulation Results: edn/edn0

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.85 %
  • code
  • 95.76 %
  • assert
  • 98.92 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.85 %
  • toggle
  • 97.07 %
  • FSM
  • 92.47 %
Validation stages
V1
100.00%
V2
98.02%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.220s 25.378us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 53.108us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.190s 24.893us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.320s 398.929us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.390s 92.480us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.580s 31.936us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.190s 24.893us 5 5 100.00
edn_csr_aliasing 1.390s 92.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 45.020s 2184.216us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 45.020s 2184.216us 100 100 100.00
genbits 100 100 100.00
edn_genbits 45.020s 2184.216us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.410s 23.651us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.660s 106.306us 200 200 100.00
errs 100 100 100.00
edn_err 1.690s 62.953us 100 100 100.00
disable 88 100 88.00
edn_disable 1.280s 12.796us 50 50 100.00
edn_disable_auto_req_mode 13.500s 500.000us 38 50 76.00
stress_all 30 30 100.00
edn_stress_all 7.890s 377.520us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.020s 86.866us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.200s 32.802us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.060s 168.867us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.060s 168.867us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.090s 53.108us 1 1 100.00
edn_csr_rw 1.190s 24.893us 5 5 100.00
edn_csr_aliasing 1.390s 92.480us 1 1 100.00
edn_same_csr_outstanding 1.430s 19.567us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.090s 53.108us 1 1 100.00
edn_csr_rw 1.190s 24.893us 5 5 100.00
edn_csr_aliasing 1.390s 92.480us 1 1 100.00
edn_same_csr_outstanding 1.430s 19.567us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.410s 1304.577us 5 5 100.00
edn_tl_intg_err 3.100s 94.577us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.230s 54.884us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.660s 106.306us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.410s 1304.577us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.410s 1304.577us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.410s 1304.577us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.410s 1304.577us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.660s 106.306us 200 200 100.00
edn_sec_cm 7.410s 1304.577us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.660s 106.306us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.100s 94.577us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 115.810s 10945.256us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 9 test runs
edn_disable_auto_req_mode 39365372075204034973903219807185966106103137244775144119855580724108022421884 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 80305838018915565684423108216662460098973065932199322966668012044436832569561 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 18232938150679482909164410672576554906182673507353705340199535737770031176190 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66007461340064224851904365115503236787033197531353833492119354094461368844229 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 115483241887018354867323434392182852578129449240686583745216544828115856457508 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 25116808760632744409923336313870673001730588113213907947856431475576147145197 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 36180435982482206695309484081701945092544390115366553071728769919320198544192 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88619849789451005859377104493547670875104818788189991740831464453783784392082 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 31975897242153108669720519083942189652833502549490084937874453656356939596368 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 7120937415641157540723087327403357944027356646326802588948517996028824503941 192
UVM_INFO @ 812585314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 31510408372869148305666880829428305362886442328520261790008921099831328338169 141
UVM_INFO @ 1264596853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 73093820308610692594912993417541550653451727431516007206891921118937175223002 369
UVM_INFO @ 4092190583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 21730335843330686995528700685100289216745902896790381111195609729323405673258 88
UVM_INFO @ 21723127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 16710737127875698311573374511752091641060180975099330178369377953070688447760 88
UVM_INFO @ 17105186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 82360469552315598255614137721214252487381411103154116416295957124192429674812 88
UVM_INFO @ 68334151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 2 test runs
edn_stress_all_with_rand_reset 29569809932454340159297213644274097713312639540119751348068099400820068975270 218
UVM_INFO @ 13211071541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 38339512205583978729708984586986722333184035129261428426066713804077254184918 148
UVM_INFO @ 10945256112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---