Simulation Results: edn/edn1

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 95.95 %
  • assert
  • 98.44 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
98.52%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.180s 21.057us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 52.621us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 0.870s 15.117us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.730s 818.620us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.270s 43.599us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.610s 120.722us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 0.870s 15.117us 5 5 100.00
edn_csr_aliasing 1.270s 43.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 99 100 99.00
edn_genbits 266.070s 10006.982us 99 100 99.00
csrng_commands 99 100 99.00
edn_genbits 266.070s 10006.982us 99 100 99.00
genbits 99 100 99.00
edn_genbits 266.070s 10006.982us 99 100 99.00
interrupts 20 20 100.00
edn_intr 1.150s 23.821us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.520s 58.199us 200 200 100.00
errs 100 100 100.00
edn_err 1.560s 30.054us 100 100 100.00
disable 92 100 92.00
edn_disable 1.010s 22.062us 50 50 100.00
edn_disable_auto_req_mode 11.690s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 8.280s 455.175us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 0.950s 12.786us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.330s 25.075us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.400s 762.025us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.400s 762.025us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.810s 52.621us 1 1 100.00
edn_csr_rw 0.870s 15.117us 5 5 100.00
edn_csr_aliasing 1.270s 43.599us 1 1 100.00
edn_same_csr_outstanding 1.250s 77.598us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.810s 52.621us 1 1 100.00
edn_csr_rw 0.870s 15.117us 5 5 100.00
edn_csr_aliasing 1.270s 43.599us 1 1 100.00
edn_same_csr_outstanding 1.250s 77.598us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.200s 1544.045us 5 5 100.00
edn_tl_intg_err 8.870s 869.460us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.120s 79.381us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.520s 58.199us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.200s 1544.045us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.200s 1544.045us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.200s 1544.045us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.200s 1544.045us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.520s 58.199us 200 200 100.00
edn_sec_cm 4.200s 1544.045us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.520s 58.199us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 8.870s 869.460us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 84.990s 8978.319us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 66350339452721214434472054476213871793800663591306950910886180541548752479391 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 52839333769886021665511496805394161624905572676411360803824538953329859762987 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 67854028619832242102088990929794349425207352760349204985466761698726852973130 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 3073609599064439410098218703744923346792730183681641526251850327399316641022 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 26298290219727054886513007117358069294874652136213144852454054244980096021037 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 115182457001937637710650696804669988696187495006649466349121174099014569304391 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 103413606653008417289951579836850956644754892122279539560065814042073998141104 222
UVM_INFO @ 1206001128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 22639834945506990629887373189523396731565682256313573544665857728178150980052 134
UVM_INFO @ 921727699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 40322595898000652902663938175231919021393441543513836289966784653200101519667 216
UVM_INFO @ 1119382740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 73372284834650456955021652412107827874384755174292483544457009146134766218001 138
UVM_INFO @ 901237609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 70481721817985410485684597347765952514756663402345471628532938342856488362002 229
UVM_INFO @ 783737665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 61283717590361605234830543067920331143563367891462374111464255647479520227812 88
UVM_INFO @ 20530682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 95637096348756299086556167668375130289610586078289324932497007438470680070864 88
UVM_INFO @ 23541504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout edn_reg_block.main_sm_state (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 1 test run
edn_genbits 75908526664221976644249406395760805852802804625031393592700280277873577537362 83
UVM_INFO @ 10006981591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---