Simulation Results

Simulation Results: flash_ctrl

01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.92 %

code
95.34 %

assert
97.02 %

func
98.39 %

line
96.09 %

branch
97.40 %

cond
94.76 %

toggle
96.60 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		99.04%
V2S		98.74%
V3		100.00%
unmapped		100.00%

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	139.750s	40.671us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	27.780s	83.738us	5	5	100.00
csr_hw_reset				1	1	100.00
	flash_ctrl_csr_hw_reset	37.090s	50.716us	1	1	100.00
csr_rw				5	5	100.00
	flash_ctrl_csr_rw	19.430s	237.578us	5	5	100.00
csr_bit_bash				1	1	100.00
	flash_ctrl_csr_bit_bash	61.900s	4099.191us	1	1	100.00
csr_aliasing				1	1	100.00
	flash_ctrl_csr_aliasing	27.920s	1303.975us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	19.990s	451.437us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	flash_ctrl_csr_rw	19.430s	237.578us	5	5	100.00
	flash_ctrl_csr_aliasing	27.920s	1303.975us	1	1	100.00
mem_walk				1	1	100.00
	flash_ctrl_mem_walk	6.290s	27.672us	1	1	100.00
mem_partial_access				1	1	100.00
	flash_ctrl_mem_partial_access	13.130s	55.735us	1	1	100.00

926/935 passed

99.04 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	27.560s	191.395us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	65.390s	275.131us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1413.250s	343547.193us	3	3	100.00
	flash_ctrl_hw_rma_reset	682.050s	160208.931us	20	20	100.00
	flash_ctrl_lcmgr_intg	14.160s	43.785us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1838.580s	295510.351us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	305.810s	22594.782us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	151.770s	6060.701us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	2960.690s	216728.630us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	92.110s	4160.065us	5	5	100.00
rd_buff_eviction_w_ecc				102	105	97.14
	flash_ctrl_rw_evict	35.020s	53.575us	37	40	92.50
	flash_ctrl_rw_evict_all_en	35.080s	43.702us	40	40	100.00
	flash_ctrl_re_evict	37.550s	245.157us	25	25	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	212.100s	1474.150us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	212.100s	1474.150us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	618.840s	57841.193us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	24.520s	719.119us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	712.720s	914.102us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	672.800s	42991.943us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	552.850s	970.530us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1377.740s	2059.977us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.920s	185.862us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	166.630s	11095.231us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	24.470s	19.175us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	18.510s	71.981us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	589.170s	277.902us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	177.230s	19004.243us	50	50	100.00
	flash_ctrl_otp_reset	122.380s	154.142us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1413.250s	343547.193us	3	3	100.00
interrupts				97	100	97.00
	flash_ctrl_intr_rd	175.070s	8219.377us	38	40	95.00
	flash_ctrl_intr_wr	3604.011s	0.000us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	342.580s	12374.253us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	334.360s	241930.501us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	71.940s	4076.093us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	76.320s	2827.069us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	25.860s	129.975us	5	5	100.00
	flash_ctrl_ro_derr	117.260s	3564.697us	10	10	100.00
	flash_ctrl_rw_derr	180.340s	2332.387us	10	10	100.00
	flash_ctrl_derr_detect	156.580s	11864.350us	5	5	100.00
	flash_ctrl_integrity	495.430s	4779.775us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	24.550s	198.766us	5	5	100.00
	flash_ctrl_ro_serr	117.560s	1713.990us	10	10	100.00
	flash_ctrl_rw_serr	153.310s	11570.378us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	59.890s	954.491us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	69.000s	5006.644us	5	5	100.00
scramble				59	62	95.16
	flash_ctrl_wo	3604.011s	0.000us	19	20	95.00
	flash_ctrl_write_word_sweep	7.330s	66.695us	1	1	100.00
	flash_ctrl_read_word_sweep	12.730s	107.014us	1	1	100.00
	flash_ctrl_ro	112.190s	754.291us	20	20	100.00
	flash_ctrl_rw	3602.873s	0.000us	18	20	90.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	35.230s	921.729us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	690.700s	40373.534us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	251.480s	10020.742us	20	20	100.00
alert_test				10	10	100.00
	flash_ctrl_alert_test	15.020s	75.247us	10	10	100.00
intr_test				10	10	100.00
	flash_ctrl_intr_test	15.160s	58.324us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	flash_ctrl_tl_errors	20.220s	116.732us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	flash_ctrl_tl_errors	20.220s	116.732us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	flash_ctrl_csr_hw_reset	37.090s	50.716us	1	1	100.00
	flash_ctrl_csr_rw	19.430s	237.578us	5	5	100.00
	flash_ctrl_csr_aliasing	27.920s	1303.975us	1	1	100.00
	flash_ctrl_same_csr_outstanding	11.510s	225.964us	5	5	100.00
tl_d_partial_access				12	12	100.00
	flash_ctrl_csr_hw_reset	37.090s	50.716us	1	1	100.00
	flash_ctrl_csr_rw	19.430s	237.578us	5	5	100.00
	flash_ctrl_csr_aliasing	27.920s	1303.975us	1	1	100.00
	flash_ctrl_same_csr_outstanding	11.510s	225.964us	5	5	100.00

V2S

469/475 passed

98.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	95.910s	95.364us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	95.910s	95.364us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	95.910s	95.364us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	95.910s	95.364us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	96.580s	1489.299us	20	20	100.00
tl_intg_err				29	30	96.67
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00
	flash_ctrl_tl_intg_err	595.540s	1728.706us	25	25	100.00
sec_cm_reg_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	595.540s	1728.706us	25	25	100.00
sec_cm_host_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	595.540s	1728.706us	25	25	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	27.140s	72.513us	3	3	100.00
	flash_ctrl_wr_intg	9.630s	346.780us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	139.750s	40.671us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	122.380s	154.142us	80	80	100.00
	flash_ctrl_disable	24.470s	19.175us	50	50	100.00
	flash_ctrl_sec_info_access	91.980s	46519.842us	50	50	100.00
	flash_ctrl_connect	18.510s	71.981us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.690s	29.296us	5	5	100.00
sec_cm_data_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	19.430s	237.578us	5	5	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	95.910s	95.364us	20	20	100.00
sec_cm_info_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	19.430s	237.578us	5	5	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	95.910s	95.364us	20	20	100.00
sec_cm_bank_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	19.430s	237.578us	5	5	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	95.910s	95.364us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	24.470s	19.175us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	27.140s	72.513us	3	3	100.00
	flash_ctrl_access_after_disable	14.970s	23.470us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	26.450s	49.183us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	24.470s	19.175us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	24.520s	719.119us	10	10	100.00
sec_cm_mem_scramble				18	20	90.00
	flash_ctrl_rw	3602.873s	0.000us	18	20	90.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	153.310s	11570.378us	10	10	100.00
	flash_ctrl_rw_derr	180.340s	2332.387us	10	10	100.00
	flash_ctrl_integrity	495.430s	4779.775us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1413.250s	343547.193us	3	3	100.00
sec_cm_ctrl_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00
sec_cm_phy_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00
sec_cm_phy_prog_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00
sec_cm_ctr_redun				4	5	80.00
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	16.810s	712.442us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				2	5	40.00
	flash_ctrl_phy_host_grant_err	13.970s	22.092us	2	5	40.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	13.100s	22.402us	5	5	100.00
sec_cm_fifo_ctr_redun				4	5	80.00
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00
sec_cm_prog_tl_lc_gate_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2439.800s	14647.460us	4	5	80.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	21.290s	231.577us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	572.610s	2926.113us	3	3	100.00

Error Messages

	Test	seed	line	log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				3 test runs
	flash_ctrl_phy_host_grant_err	42777800917910340683648127239997085757074505167094008711051376937101053195	125	UVM_ERROR @ 24945.3 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 24945.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	31210113557911754836256848438177707176717753125100009896244915522496252860485	125	UVM_ERROR @ 22680.4 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 22680.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	19650157466968862289361390134831801731988298139008603897396374220538769929169	125	UVM_ERROR @ 22092.0 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 22092.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	flash_ctrl_intr_wr	46065107371008680604353467667684995041343689817910629559028207918389169132818	None
	flash_ctrl_wo	105619024332737268221211838242637717844901206445897541458760801811622552609203	None
	flash_ctrl_rw	39093540310888297566575116977196368611444622925699186234549056036464784987783	None
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				2 test runs
	flash_ctrl_rw_evict	104987717764021417550154227862971123652668412084574625076191762984812659929927	108	UVM_INFO @ 32741.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	97566102861528816433296926420629273483426425597981830749829453632407424587022	108	UVM_INFO @ 49400.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{:}				1 test run
	flash_ctrl_sec_cm	59808832092431439907390590346610804450636932785691518750675226239375159284102	1011	UVM_INFO @ 366416.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly				1 test run
	flash_ctrl_rw	91016324837729394760191751627445595606821661848191379024709042410091450506251	108	UVM_INFO @ 2178592.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:				1 test run
	flash_ctrl_rw_evict	4128347615442714639882611563819947354582865357273587527213563266982035513046	108	UVM_INFO @ 69357.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp b293b168_caa4bb0f:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	105327530320534750557875916520001953155017056442004308544213386363415549581489	108	UVM_INFO @ 16297657.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp c1220ae7_bda0822a:ffffffff_bda0822a mismatch!!				1 test run
	flash_ctrl_intr_rd	50201962630346923863077599798326987292821934082636057998835965458403676337380	108	UVM_INFO @ 3331482.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---