Simulation Results: hmac

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.61 %
  • code
  • 98.61 %
  • assert
  • 97.60 %
  • func
  • 99.62 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.890s 1368.131us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.140s 164.113us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.300s 33.162us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.170s 8145.681us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.950s 103.327us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 219.890s 52521.919us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.300s 33.162us 5 5 100.00
hmac_csr_aliasing 3.950s 103.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 91.230s 10668.101us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 90.770s 4647.755us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 268.380s 40551.412us 30 30 100.00
hmac_test_sha384_vectors 567.990s 96943.247us 75 75 100.00
hmac_test_sha512_vectors 563.820s 21998.846us 75 75 100.00
hmac_test_hmac256_vectors 15.850s 466.689us 50 50 100.00
hmac_test_hmac384_vectors 18.500s 503.674us 60 60 100.00
hmac_test_hmac512_vectors 19.330s 523.541us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 53.890s 6387.431us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1263.580s 8999.854us 10 10 100.00
error 10 10 100.00
hmac_error 83.300s 2329.519us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 98.630s 34125.952us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.890s 1368.131us 10 10 100.00
hmac_long_msg 91.230s 10668.101us 10 10 100.00
hmac_back_pressure 90.770s 4647.755us 25 25 100.00
hmac_datapath_stress 1263.580s 8999.854us 10 10 100.00
hmac_burst_wr 53.890s 6387.431us 50 50 100.00
hmac_stress_all 4766.480s 432425.042us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.890s 1368.131us 10 10 100.00
hmac_long_msg 91.230s 10668.101us 10 10 100.00
hmac_back_pressure 90.770s 4647.755us 25 25 100.00
hmac_datapath_stress 1263.580s 8999.854us 10 10 100.00
hmac_wipe_secret 98.630s 34125.952us 10 10 100.00
hmac_test_sha256_vectors 268.380s 40551.412us 30 30 100.00
hmac_test_sha384_vectors 567.990s 96943.247us 75 75 100.00
hmac_test_sha512_vectors 563.820s 21998.846us 75 75 100.00
hmac_test_hmac256_vectors 15.850s 466.689us 50 50 100.00
hmac_test_hmac384_vectors 18.500s 503.674us 60 60 100.00
hmac_test_hmac512_vectors 19.330s 523.541us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.890s 1368.131us 10 10 100.00
hmac_long_msg 91.230s 10668.101us 10 10 100.00
hmac_back_pressure 90.770s 4647.755us 25 25 100.00
hmac_datapath_stress 1263.580s 8999.854us 10 10 100.00
hmac_burst_wr 53.890s 6387.431us 50 50 100.00
hmac_error 83.300s 2329.519us 10 10 100.00
hmac_wipe_secret 98.630s 34125.952us 10 10 100.00
hmac_test_sha256_vectors 268.380s 40551.412us 30 30 100.00
hmac_test_sha384_vectors 567.990s 96943.247us 75 75 100.00
hmac_test_sha512_vectors 563.820s 21998.846us 75 75 100.00
hmac_test_hmac256_vectors 15.850s 466.689us 50 50 100.00
hmac_test_hmac384_vectors 18.500s 503.674us 60 60 100.00
hmac_test_hmac512_vectors 19.330s 523.541us 75 75 100.00
hmac_stress_all 4766.480s 432425.042us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 4766.480s 432425.042us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.940s 26.790us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.990s 16.841us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.620s 4631.500us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.620s 4631.500us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.140s 164.113us 1 1 100.00
hmac_csr_rw 1.300s 33.162us 5 5 100.00
hmac_csr_aliasing 3.950s 103.327us 1 1 100.00
hmac_same_csr_outstanding 2.890s 523.478us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.140s 164.113us 1 1 100.00
hmac_csr_rw 1.300s 33.162us 5 5 100.00
hmac_csr_aliasing 3.950s 103.327us 1 1 100.00
hmac_same_csr_outstanding 2.890s 523.478us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.430s 96.573us 5 5 100.00
hmac_tl_intg_err 4.870s 278.345us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.870s 278.345us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.890s 1368.131us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.520s 115.945us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 944.960s 116317.063us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.050s 53.580us 1 1 100.00