Simulation Results: keymgr

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.89 %
  • code
  • 98.86 %
  • assert
  • 97.72 %
  • func
  • 91.10 %
  • line
  • 99.20 %
  • branch
  • 99.18 %
  • cond
  • 98.24 %
  • toggle
  • 97.68 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.30%
V2S
99.38%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 3.310s 251.379us 30 30 100.00
random 30 30 100.00
keymgr_random 4.350s 425.332us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.180s 83.606us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.350s 32.977us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 15.160s 2992.384us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.070s 328.888us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.850s 61.840us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.350s 32.977us 5 5 100.00
keymgr_csr_aliasing 3.070s 328.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 3.840s 313.043us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 2.860s 342.313us 20 20 100.00
keymgr_sideload_kmac 3.070s 91.363us 20 20 100.00
keymgr_sideload_aes 2.980s 823.545us 20 20 100.00
keymgr_sideload_otbn 3.070s 798.095us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 3.220s 131.980us 30 30 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 5.060s 180.231us 49 50 98.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 3.930s 612.335us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 6.150s 233.324us 20 20 100.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 3.990s 537.159us 49 50 98.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 2.540s 219.807us 20 20 100.00
stress_all 49 50 98.00
keymgr_stress_all 40.640s 1728.054us 49 50 98.00
intr_test 10 10 100.00
keymgr_intr_test 0.880s 80.546us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 0.960s 12.805us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 3.710s 301.207us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 3.710s 301.207us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.180s 83.606us 1 1 100.00
keymgr_csr_rw 1.350s 32.977us 5 5 100.00
keymgr_csr_aliasing 3.070s 328.888us 1 1 100.00
keymgr_same_csr_outstanding 2.980s 95.532us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.180s 83.606us 1 1 100.00
keymgr_csr_rw 1.350s 32.977us 5 5 100.00
keymgr_csr_aliasing 3.070s 328.888us 1 1 100.00
keymgr_same_csr_outstanding 2.980s 95.532us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
keymgr_tl_intg_err 6.520s 1048.216us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 3.240s 1026.971us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 3.240s 1026.971us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 3.240s 1026.971us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 3.240s 1026.971us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 10.230s 1131.434us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 6.520s 1048.216us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 3.240s 1026.971us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 3.840s 313.043us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 4.350s 425.332us 30 30 100.00
keymgr_csr_rw 1.350s 32.977us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 4.350s 425.332us 30 30 100.00
keymgr_csr_rw 1.350s 32.977us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 4.350s 425.332us 30 30 100.00
keymgr_csr_rw 1.350s 32.977us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 5.060s 180.231us 49 50 98.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 3.990s 537.159us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 3.990s 537.159us 49 50 98.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 4.350s 425.332us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 3.150s 344.235us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 4.260s 224.007us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 5.060s 180.231us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 4.260s 224.007us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 4.260s 224.007us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 4.260s 224.007us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.610s 1167.787us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 4.260s 224.007us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 14 20 70.00
keymgr_stress_all_with_rand_reset 13.740s 861.229us 14 20 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
keymgr_stress_all_with_rand_reset 17123588658483522280530598049475998718285415266086538178543442690571644124224 367
UVM_INFO @ 440887162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 100826358512303157637487979205583413311503825790641912438830009617624294243920 926
UVM_INFO @ 883562862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 91087595561159028600160205876429189072787790161235803476984736037613093485573 771
UVM_INFO @ 823956015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 27282302762668226511470455696569089533948738392705091838717596249152493865244 1545
UVM_INFO @ 1367629752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 27444734214381094867020540144755552670705666324667675481487140041157017315714 654
UVM_INFO @ 2079318698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 108140106956220466460851919926344315443825615024371816287934708803579726720217 473
UVM_INFO @ 2196092696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 2 test runs
keymgr_stress_all 87706960603855103246403895427707262334462259755820433923075044823972966906738 919
UVM_INFO @ 1131446862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_hwsw_invalid_input 48393541326401142503416241370643037146819936343108965157270181921868313000510 138
UVM_INFO @ 106569189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:778) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_lc_disable 67651470456019735238474958760469838974193584707042039573392100166020958651630 209
UVM_INFO @ 61909049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---