Simulation Results: lc_ctrl/volatile_unlock_disabled

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.18 %
  • code
  • 85.93 %
  • assert
  • 94.55 %
  • func
  • 96.06 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.84 %
  • toggle
  • 88.33 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.30%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.200s 247.479us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.280s 73.110us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.280s 92.063us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.510s 101.562us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 28.434us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.480s 23.645us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.280s 92.063us 5 5 100.00
lc_ctrl_csr_aliasing 1.530s 28.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.200s 161.182us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.800s 1635.454us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.160s 20.988us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.400s 943.732us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 11.970s 7112.401us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_prog_failure 3.400s 943.732us 20 20 100.00
lc_ctrl_errors 11.970s 7112.401us 19 20 95.00
lc_ctrl_security_escalation 7.790s 1546.651us 20 20 100.00
lc_ctrl_jtag_state_failure 47.610s 17091.458us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.000s 5687.108us 20 20 100.00
lc_ctrl_jtag_errors 72.770s 13383.976us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 8.110s 2744.825us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.640s 982.090us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.000s 5687.108us 20 20 100.00
lc_ctrl_jtag_errors 72.770s 13383.976us 19 20 95.00
lc_ctrl_jtag_access 9.520s 618.544us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 16.550s 2475.614us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.790s 434.180us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.380s 114.634us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.840s 5534.539us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 6.920s 1123.037us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.840s 173.962us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.450s 161.600us 10 10 100.00
lc_ctrl_jtag_alert_test 2.270s 505.575us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 20.960s 11134.210us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.280s 58.504us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 335.930s 19212.643us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.290s 27.267us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.570s 371.364us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.570s 371.364us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 73.110us 1 1 100.00
lc_ctrl_csr_rw 1.280s 92.063us 5 5 100.00
lc_ctrl_csr_aliasing 1.530s 28.434us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 18.285us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 73.110us 1 1 100.00
lc_ctrl_csr_rw 1.280s 92.063us 5 5 100.00
lc_ctrl_csr_aliasing 1.530s 28.434us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 18.285us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
lc_ctrl_tl_intg_err 3.060s 549.660us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.060s 549.660us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.800s 1635.454us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.490s 1797.537us 20 20 100.00
lc_ctrl_sec_cm 8.940s 284.807us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.790s 1546.651us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 8.200s 161.182us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.640s 982.090us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.670s 884.835us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.670s 884.835us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.010s 533.049us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.230s 1154.470us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.230s 1154.470us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 73.860s 10992.939us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 88350889997996266039589723626584616758445852226759330777949425182913662603310 2715
UVM_INFO @ 2242261662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 97139560594830318126856121623372449064730300306196132754546678591746313249907 151
UVM_INFO @ 216233450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60610449103597623045546958637031779599943383557200392113551730669601371066946 5700
UVM_INFO @ 2668009300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51222744569485928856708981582697385816803325927749471454739527023763699261263 12985
UVM_INFO @ 4318738817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92869085082754140132408522112753500869111402371115661535849762966287358495940 271
UVM_INFO @ 8801388209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 62018061591383680300366507678747569971493129405924166014725201366610870792510 1966
UVM_INFO @ 9431177090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_jtag_errors 34079433570590979681791418224241043254238022267314365156598023959198698754180 2947
UVM_INFO @ 5587302219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 31036051996278807944194640106555639622723922846875083437141527498099309959211 3870
UVM_INFO @ 591177370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 112213964391548810072003731345384932752634257695045308183553833418237013563946 924
UVM_INFO @ 590919502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---