Simulation Results: lc_ctrl/volatile_unlock_enabled

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.20 %
  • code
  • 86.02 %
  • assert
  • 94.69 %
  • func
  • 95.88 %
  • line
  • 97.26 %
  • branch
  • 93.95 %
  • cond
  • 81.41 %
  • toggle
  • 88.33 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 2.930s 140.302us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.200s 31.277us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.240s 31.770us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.850s 286.577us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.400s 167.078us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.680s 23.380us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.240s 31.770us 5 5 100.00
lc_ctrl_csr_aliasing 1.400s 167.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.080s 292.057us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.380s 552.324us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.180s 13.956us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.610s 711.944us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 10.800s 2214.873us 20 20 100.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_prog_failure 3.610s 711.944us 20 20 100.00
lc_ctrl_errors 10.800s 2214.873us 20 20 100.00
lc_ctrl_security_escalation 11.110s 605.521us 20 20 100.00
lc_ctrl_jtag_state_failure 39.490s 8222.377us 20 20 100.00
lc_ctrl_jtag_prog_failure 8.710s 2668.986us 20 20 100.00
lc_ctrl_jtag_errors 41.630s 4817.516us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 6.490s 1461.966us 20 20 100.00
lc_ctrl_jtag_state_post_trans 16.260s 678.336us 20 20 100.00
lc_ctrl_jtag_prog_failure 8.710s 2668.986us 20 20 100.00
lc_ctrl_jtag_errors 41.630s 4817.516us 18 20 90.00
lc_ctrl_jtag_access 7.910s 956.187us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 15.380s 2491.652us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.420s 170.892us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.030s 202.791us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.960s 2119.049us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 6.520s 1679.816us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.770s 180.870us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.820s 551.431us 10 10 100.00
lc_ctrl_jtag_alert_test 1.590s 742.786us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 8.150s 682.537us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.300s 19.850us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 137.980s 10239.607us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.320s 23.607us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.530s 178.714us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.530s 178.714us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.200s 31.277us 1 1 100.00
lc_ctrl_csr_rw 1.240s 31.770us 5 5 100.00
lc_ctrl_csr_aliasing 1.400s 167.078us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.760s 338.132us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.200s 31.277us 1 1 100.00
lc_ctrl_csr_rw 1.240s 31.770us 5 5 100.00
lc_ctrl_csr_aliasing 1.400s 167.078us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.760s 338.132us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
lc_ctrl_tl_intg_err 3.020s 326.647us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.020s 326.647us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.380s 552.324us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 11.410s 2146.613us 20 20 100.00
lc_ctrl_sec_cm 7.660s 512.093us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.110s 605.521us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.080s 292.057us 20 20 100.00
lc_ctrl_jtag_state_post_trans 16.260s 678.336us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.460s 2920.312us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.460s 2920.312us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 6.920s 476.379us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.810s 462.564us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.810s 462.564us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
lc_ctrl_stress_all_with_rand_reset 70.540s 3659.667us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
lc_ctrl_stress_all_with_rand_reset 18421337995670358559291015035945224695731504110100832005403274731091915485125 5153
UVM_INFO @ 3804013697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28880163708278743160124678519364738086514565396114888853863714076896029849909 5904
UVM_INFO @ 3203990520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 7722387824980980217700324905700784674921972340025138728770813984881072848695 565
UVM_INFO @ 1094190247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 45493755445406996331313241324481657208697399985644774747303031345640820124255 1301
UVM_INFO @ 9425722757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 49533010655456091558785538250079406638312780732583165872319775192485060730160 357
UVM_INFO @ 96519644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---