Simulation Results: otbn

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.25 %
  • code
  • 82.81 %
  • assert
  • 96.94 %
  • func
  • 100.00 %
  • block
  • 97.85 %
  • line
  • 98.03 %
  • branch
  • 82.61 %
  • toggle
  • 83.00 %
  • FSM
  • 67.61 %
Validation stages
V1
99.14%
V2
99.39%
V2S
98.18%
V3
10.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 38.000s 57.708us 1 1 100.00
single_binary 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 35.000s 21.089us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 34.000s 17.695us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 37.000s 80.259us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 34.000s 73.898us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 251.837us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 34.000s 17.695us 5 5 100.00
otbn_csr_aliasing 34.000s 73.898us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 105.000s 2816.598us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 47.000s 1092.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 65.000s 211.482us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 85.000s 385.073us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 169.000s 1824.465us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 167.000s 1285.171us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 363.000s 2550.597us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 11.076us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 146.000s 935.304us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 35.000s 53.129us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 34.000s 91.514us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 25.000s 43.192us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 25.000s 43.192us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 35.000s 21.089us 1 1 100.00
otbn_csr_rw 34.000s 17.695us 5 5 100.00
otbn_csr_aliasing 34.000s 73.898us 1 1 100.00
otbn_same_csr_outstanding 33.000s 35.051us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 35.000s 21.089us 1 1 100.00
otbn_csr_rw 34.000s 17.695us 5 5 100.00
otbn_csr_aliasing 34.000s 73.898us 1 1 100.00
otbn_same_csr_outstanding 33.000s 35.051us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 39.000s 18.296us 10 10 100.00
otbn_dmem_err 38.000s 39.044us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 38.000s 222.132us 5 5 100.00
otbn_controller_ispr_rdata_err 39.000s 64.700us 5 5 100.00
otbn_mac_bignum_acc_err 37.000s 115.880us 5 5 100.00
otbn_urnd_err 18.000s 14.357us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 35.000s 83.348us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 39.000s 31.967us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 36.000s 24.734us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
otbn_tl_intg_err 66.000s 390.597us 25 25 100.00
passthru_mem_tl_intg_err 3 5 60.00
otbn_passthru_mem_tl_intg_err 83.000s 1810.879us 3 5 60.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 38.000s 57.708us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 38.000s 39.044us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 39.000s 18.296us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 66.000s 390.597us 25 25 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 363.000s 2550.597us 60 60 100.00
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 39.000s 18.296us 10 10 100.00
otbn_dmem_err 38.000s 39.044us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 11.076us 5 5 100.00
otbn_illegal_mem_acc 35.000s 83.348us 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 39.000s 18.296us 10 10 100.00
otbn_dmem_err 38.000s 39.044us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 11.076us 5 5 100.00
otbn_illegal_mem_acc 35.000s 83.348us 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 363.000s 2550.597us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 39.000s 18.296us 10 10 100.00
otbn_dmem_err 38.000s 39.044us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 11.076us 5 5 100.00
otbn_illegal_mem_acc 35.000s 83.348us 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 34.000s 24.478us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 35.000s 13.793us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 51.000s 858.205us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 51.000s 858.205us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 37.000s 34.090us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 39.000s 183.925us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 31.000s 32.469us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 31.000s 32.469us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 32.000s 30.318us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 169.000s 1824.465us 9 10 90.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 25.000s 26.075us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 94.000s 398.573us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 766.000s 3213.420us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
otbn_stress_all_with_rand_reset 360.000s 2924.959us 1 10 10.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 32.000s 21.044us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
otbn_stress_all_with_rand_reset 45578957481490580555107706778112446981158692563085736245941042285921152963997 246
UVM_INFO @ 1361964213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 61422551097331704649695084187245367260116754492862100809928742914977805175652 156
UVM_INFO @ 461981869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 50019137266569720058727165310996887921554207083673908705429646684076557846763 164
UVM_INFO @ 530649850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 70892068931479754406678497759020691339161729009696685308184008496641139035055 302
UVM_INFO @ 2924958920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 111724147364540221046285872686839432043818710753191779999804040297250086603194 168
UVM_INFO @ 1091633676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 20258585446917552561269839128935986610813009791213274173387684486106830273528 158
UVM_INFO @ 123156355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 89025437458781761517940085629658987340996056121238770588361420621282625830246 292
UVM_INFO @ 2452364186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 31872970839831785619455742936655190818693905036882685896448093623346673573660 283
UVM_INFO @ 1467830875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 3 test runs
otbn_multi 110578691956296566353130627154292510747530713207773250736121392969411584119047 181
UVM_INFO @ 367830516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 6203429650924831901288647070598751334353949812828700287739305861628854558762 116
UVM_INFO @ 136952450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_single 25551015210493054320788193915187872602811520782783685337118840839138770887136 108
UVM_INFO @ 83764309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 106595148019328531556998032094959911490399531417460697310558526944068224292800 86
UVM_INFO @ 1250558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,173): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_partial_wipe 54593247456544857266264469372467647517735483902400528432971480730881773987588 107
UVM_ERROR @ 7768883 ps: (otbn_idle_checker.sv:173) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 7768883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:138) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) 1 test run
otbn_rf_base_intg_err 107425218963406368373039290589763922518889739337562192972974170561550094265577 115
UVM_INFO @ 30770204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 51682772723292658973952444555822783058224570057165651173683710162482842724428 431
UVM_INFO @ 1342896440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---