Simulation Results: otp_ctrl

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.12 %
  • code
  • 85.44 %
  • assert
  • 95.47 %
  • func
  • 92.45 %
  • line
  • 90.16 %
  • branch
  • 86.66 %
  • cond
  • 94.00 %
  • toggle
  • 92.68 %
  • FSM
  • 63.72 %
Validation stages
V1
96.15%
V2
94.69%
V2S
94.09%
V3
23.76%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.920s 809.940us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 21.730s 3041.514us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.420s 115.746us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.220s 630.898us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.160s 587.595us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.330s 187.144us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.300s 433.047us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.220s 630.898us 5 5 100.00
otp_ctrl_csr_aliasing 5.330s 187.144us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.490s 84.844us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.550s 143.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 16.040s 1665.122us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 7.070s 1696.062us 300 300 100.00
partition_check 28 60 46.67
otp_ctrl_background_chks 29.690s 16017.136us 10 10 100.00
otp_ctrl_check_fail 48.770s 10002.547us 18 50 36.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 8.810s 2907.032us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 38.160s 17277.185us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 24.760s 1261.272us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 28.990s 12282.396us 10 10 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
otp_dai_errors 24 25 96.00
otp_ctrl_dai_errs 47.900s 17063.575us 24 25 96.00
otp_macro_errors 3 10 30.00
otp_ctrl_macro_errs 12.840s 8934.954us 3 10 30.00
test_access 10 10 100.00
otp_ctrl_test_access 38.470s 20921.025us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 192.100s 11669.828us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.720s 576.180us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.020s 755.738us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 6.950s 2325.252us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 6.950s 2325.252us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.420s 115.746us 1 1 100.00
otp_ctrl_csr_rw 2.220s 630.898us 5 5 100.00
otp_ctrl_csr_aliasing 5.330s 187.144us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.770s 278.745us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.420s 115.746us 1 1 100.00
otp_ctrl_csr_rw 2.220s 630.898us 5 5 100.00
otp_ctrl_csr_aliasing 5.330s 187.144us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.770s 278.745us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
otp_ctrl_tl_intg_err 33.000s 20471.788us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 33.000s 20471.788us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 21.730s 3041.514us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 21.730s 3041.514us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
sec_cm_part_fsm_local_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
otp_ctrl_macro_errs 12.840s 8934.954us 3 10 30.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
sec_cm_part_fsm_global_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
otp_ctrl_macro_errs 12.840s 8934.954us 3 10 30.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 32.530s 11849.078us 200 200 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 7.070s 1696.062us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 18 50 36.00
otp_ctrl_check_fail 48.770s 10002.547us 18 50 36.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 38.160s 17277.185us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 38.160s 17277.185us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 38.160s 17277.185us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 38.160s 17277.185us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 38.160s 17277.185us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 21.730s 3041.514us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 38.160s 17277.185us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 21.730s 3041.514us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 242.300s 157327.529us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 8.810s 2907.032us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 21.730s 3041.514us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 21.730s 3041.514us 10 10 100.00
sec_cm_macro_mem_integrity 3 10 30.00
otp_ctrl_macro_errs 12.840s 8934.954us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.830s 3563.539us 1 1 100.00
stress_all_with_rand_reset 23 100 23.00
otp_ctrl_stress_all_with_rand_reset 132.280s 5254.884us 23 100 23.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 51 test runs
otp_ctrl_check_fail 104155906680120152196659555821935559446905067453108176752541544497832261302709 535
UVM_INFO @ 911477290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 90772067553366662184945690469743530717539330256871205976650900778096835077410 2184
UVM_INFO @ 900066370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 17479869634760537097021840271990319906122118821041764261873275050270988245798 1236
UVM_INFO @ 555613991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 3813426517046940030428127859845740468571379662060081121059351851832771829483 8124
UVM_INFO @ 11602750787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 32897524641122900683991757656565859391061499029880887760139611597599144530596 4400
UVM_INFO @ 8934954388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 89296622811796123198345361558863802536976099151703430205442337254461668283659 2231
UVM_INFO @ 179779138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 90719983955586826869218922453542469221940792918668677055314355450261066841488 263
UVM_INFO @ 44240789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26017806158444036031622170659964301314463278227398660765457814472137857476369 153
UVM_INFO @ 565908901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 21649771087496126938851743173534438210311415762497015274283621617651041706855 839
UVM_INFO @ 1489095516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 78742679608579509746219889454605422023674718413844129096123074423125726316371 409
UVM_INFO @ 1106476987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 94130789466800568318009761786055512323476111656676288600682463733935444812010 267
UVM_INFO @ 69141414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73419305101308823946806047560095495552606491284152420474739438936792674048466 5537
UVM_INFO @ 902857766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 38623969520818827818246881241391280588660930269939372477565106892932026886811 5745
UVM_INFO @ 242116862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 65897227723061449970559578601278150348330318139433284336470633617640988703115 10938
UVM_INFO @ 913110977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 30259914530929047689526888697780760322864887310911049284765359216162522476076 2870
UVM_INFO @ 707742252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 12261182800400099427093927595365003805484693789710560223155273480898904886920 986
UVM_INFO @ 2949573207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70560560007423874128305188313895141887226089496116932735833099190930471285685 188
UVM_INFO @ 1075945584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 45980059734172506171429421939026062910579171107897451060205426164844977426032 2314
UVM_INFO @ 377712521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37298205022857963677173924473452363759204022780981644408645310572533735209986 3785
UVM_INFO @ 5377682819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 114363175484817608371547436739767707367443008210266283815471991357463668389132 8179
UVM_INFO @ 4079511672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 96349234852838038166067379685359334552900725577338283239408180333046991140027 2137
UVM_INFO @ 2919433786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 27506683055099789235545525287728675645947099456354390340154588735112950074942 9174
UVM_INFO @ 1201634451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72616542161419334718975050198345180384955103645909780990069377165524447749311 4419
UVM_INFO @ 1156012185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 9021596886785339831731305673445679344582452656607566881119006075995840699716 6148
UVM_INFO @ 2695323269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85768462380399303156538725104714322106923528639184452652003780302261566149967 3907
UVM_INFO @ 2394156307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 35840848035637164427778702468103144704175260617929343131793171276709672183776 5876
UVM_INFO @ 1134627936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17659699637354742272540175184413347466991437932410881190231768534904163666733 5964
UVM_INFO @ 766645989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 62840542027975616348027938671771000570053339296503115115131433760356171578515 9591
UVM_INFO @ 20188279937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 63051871828605433136651955464155006130150123900329501656471317518182747345176 2408
UVM_INFO @ 127062705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 4887243174123304191462518426377147025842713950713220380076232388755692050869 5187
UVM_INFO @ 6726656249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 833582072910926785452728779066287864129148657972292062359532011234950004287 897
UVM_INFO @ 1542926176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 114197818527787118798699830092641910275835890809251571709325757285385518433876 490
UVM_INFO @ 188064276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35955573870833319772779277698892491521109532947980519578094333915588597831962 8243
UVM_INFO @ 2184958495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 6274597878424272292252665674271574604179805773951684295261520687186305872826 1231
UVM_INFO @ 54271598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 37867156648646396888607130051415991437216667973678617326671946693305253075062 353
UVM_INFO @ 60478472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 51355343097898474509196211383902860264570163962674214200319897417827472309995 4062
UVM_INFO @ 5878637178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88057166957376564836065198342138980084734145095968986320089153838331572590968 6848
UVM_INFO @ 7748554719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 99760045677704429809994407621374942930034498828247587712583361126060248629849 7426
UVM_INFO @ 808037107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 63575703569481130403199143501296947082161411939117950613279524287166888527740 701
UVM_INFO @ 127757369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39661003967068456909115970949023202515345504490869872757430494314092773383088 147
UVM_INFO @ 78672791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17187174499652654981903816141373249691621501127521412426820632072225130084077 1750
UVM_INFO @ 484094050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 96316457020083546058972659022153491965523389847227718333644421593547052250877 10673
UVM_INFO @ 1915690592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85896837323510185067499397605508758369795242213761095688901130546345866511312 2264
UVM_INFO @ 491369697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 69407543933890896550266703828927824949204107191440543698023154734103750219330 11795
UVM_INFO @ 964448595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26863013785156303863184666480742310913878592678736335146454863636252785696710 907
UVM_INFO @ 73455196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 48062801603189875813484683768412021875597767055358025285726905417693511466829 13764
UVM_INFO @ 1415282752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86773738973925678141381788389574130300727915450253583691764510161062133299148 5079
UVM_INFO @ 168345011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 67460221969819947914671103829437067803018306444810893493420061361668728477920 393
UVM_INFO @ 212658530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28326678542226861303232615000344356700879553040129213958095308524043228809556 10902
UVM_INFO @ 3121939738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100861933065012816331638067529029330247760169058830977391013380927498516928985 1432
UVM_INFO @ 950417595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73741868992210003062671886040093904765878327348162055712732555758346432308094 13442
UVM_INFO @ 1648693909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1831) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 23 test runs
otp_ctrl_stress_all_with_rand_reset 10336655782567845001976000608885546778448011884219827634039782199896416613691 56199
UVM_INFO @ 24864891783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73344217432297880811935806370476388022845912699605236417750842741383492942609 92
UVM_INFO @ 28793772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63107268286912780184601564017184218927847061779666505810532672299341225428622 3924
UVM_INFO @ 2831054575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112179923853463126624230353421066675347904796713819010203653363510800421746597 4167
UVM_INFO @ 633181288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9216980396880343211768030187094030335933075441146984682871418799227398283611 476
UVM_INFO @ 12865857885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35741196832524465919540290416263439277024361784418209800196308478180836526534 1949
UVM_INFO @ 3599008608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13230202281863924999969224380221989387940600718884315116671216995656019820345 11332
UVM_INFO @ 26288391052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34812098960112209005008225790456600454931359604248714947317132049407920563171 6122
UVM_INFO @ 316029359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40458433545738805262469784968668091372614018926800356467399160334632453193048 93
UVM_INFO @ 431562233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82150793385693703290610685136499520665096748470449849127800316371955764492915 10605
UVM_INFO @ 3700802189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6791077233292103145357471151316633882090325632355437855136140538117073970887 24259
UVM_INFO @ 4004029303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10275182060075154504179082898465335631031414960575952965236187237446460766644 268
UVM_INFO @ 4751905285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109531834011296432380904215439028057326459971721775012583334977452926366550848 92
UVM_INFO @ 51192044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105441166910831804129477247885951012560196501600829287576763256538158753430533 7501
UVM_INFO @ 1834616590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12703989451128526356945195779534590902539362488295573159583126651601937640155 14650
UVM_INFO @ 457318195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75029366021854030974124839570559114460619117441134436792277957072982302358624 33949
UVM_INFO @ 1026999866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2586003842292804782470705585058746720022866611116890639911328178798655536097 31975
UVM_INFO @ 7656679054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27829371969682719232243815878877470223656652035665838825239727587668500429116 27570
UVM_INFO @ 17026991510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77851065743308240173394463557550282197290978859522467091724185803474198181246 92
UVM_INFO @ 426743864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55302942337808936855975451387221883454052234850336265826552724693433248074025 92
UVM_INFO @ 29829829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57081081257307437733899688952689297197462188735590473448501210682898857852154 14946
UVM_INFO @ 7519291266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44376492181815310035060602697587439307052024601814074426146367457425120397747 190
UVM_INFO @ 10458415645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109774756551368803738200154920847323899236994208234448064192400721253363532006 2436
UVM_INFO @ 977436524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 20 test runs
otp_ctrl_stress_all_with_rand_reset 53713554545277712250430868975731691329411648367199503999050450225377799980123 7228
UVM_INFO @ 4546434735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90122856547879888640606251949262367920684211583628061964012725347882108661357 4549
UVM_INFO @ 1254292327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112407749991528342625041916286273862335793669870163271651253002512746028853630 172
UVM_INFO @ 219742780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82275331151229545180363972486715832313386774196414335331836784032964629010175 6120
UVM_INFO @ 15883459895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109958439123765341091723934352768264970019627423547545450642602845306225598596 5401
UVM_INFO @ 16661246061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70795763356756991654009637475061656321005499519579936582409719118024584439871 4222
UVM_INFO @ 4255934300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28624119020860837107908612493484209023767372164298151684742748514067542139865 8024
UVM_INFO @ 30180398201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1113761151753868565097538445236212200087194792130969030476184850874967138550 149
UVM_INFO @ 61373651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49198401500967229377465999602569800751700056445858793080498219130468228004047 463
UVM_INFO @ 2143675881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110860491857252909429802612028769351416106044573164424019999022135144545628643 18089
UVM_INFO @ 4554300437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16477803508505341182774233751001239155993089502732349307320068644540386012129 2616
UVM_INFO @ 5155240966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74476716451200081013405625740561699407657352333729829325400966845437846263532 6995
UVM_INFO @ 1900507923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37245595526439698714551764433531898585042378482768780402689598044987167420165 1047
UVM_INFO @ 3647621430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22112870575364624878385190619637152347242832165769902461059693848727785886156 8984
UVM_INFO @ 8025961802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60404597682370460262933461936223212141369505586250304320337064697633009330540 37532
UVM_INFO @ 2030331521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96652224881513809907869753070216890418773174863816288429895681984108023488622 3038
UVM_INFO @ 34304835298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23101433131079644019048839378570631580935508904961058573247970600911754811021 863
UVM_INFO @ 426874307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23194695321823451124226150179286299614369013973565159833311989636330778547636 16986
UVM_INFO @ 2538959993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43759396941472704084505819677939872374819406560536788028019742999752475877184 7264
UVM_INFO @ 2279958616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10696495791044412166162932570457307826567249633294714771040597114325724608828 469
UVM_INFO @ 259913639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 11 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 80046235754677131654020394341218595187158552104966550780871182090640483773473 98
UVM_INFO @ 239791903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90244991884746854421938192574341895289095303229399331063590168294382232933754 17344
UVM_INFO @ 1401296821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51717394147117377453720604186388051571822108974476327777000651167910224808891 3857
UVM_INFO @ 13639221870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68842784007276033074082932144405498707531926603172028433322888916066089663567 19007
UVM_INFO @ 3242069399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44756460912596915420313789231448736497783755023030970468970854093102294819901 2373
UVM_INFO @ 560835029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103597456657338177477909121449044699898430497319680114607612353271204338280744 3889
UVM_INFO @ 1536151410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43626728821487397185401813136583107562024272760480317899040949581028439477426 2563
UVM_INFO @ 10009289346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55721761895957710130242164558939560466278165800806883008340383744634425919479 5922
UVM_INFO @ 443522127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72571750803038764757599063442715011127098302871437192361994385985251474881202 9569
UVM_INFO @ 12025500489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86471324675863346957106342562251580477535701956876860299582376072225492829605 92
UVM_INFO @ 26721044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107405498342936985024303014227617233395456574534381263683139105434420167489989 223
UVM_INFO @ 5004765788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 3 test runs
otp_ctrl_stress_all_with_rand_reset 99406373648715542563797139446287576401609332563627216160202741429803809801019 262
UVM_INFO @ 137298781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35833804694804920761947327805433045646725013943164559851721411039210709293848 9541
UVM_INFO @ 3261580246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81930433212944866112735354689830057380332665342408189603066154124415686150404 15185
UVM_INFO @ 39435347826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 2 test runs
otp_ctrl_stress_all_with_rand_reset 85379251402072414521459971741946203108068005006563583396518517182615407958167 339
UVM_INFO @ 3578143898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4974678360813037126115211155256484075798849341428934117599520415268315170211 148
UVM_INFO @ 25655661341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_stress_all_with_rand_reset 63567751303507681217122855375319203251303790418841698538297484169191157809799 93
UVM_ERROR @ 53420247 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 53420247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35990668411431543294300302166065729411095257390448321307330031420670999258347 15405
UVM_ERROR @ 41016241979 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 41016241979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
otp_ctrl_stress_all_with_rand_reset 62372799489347717822282931501893076353935409899049748962483779475445506661962 8369
UVM_INFO @ 6764202732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27616514481224671670943246194298704122833335169458464263504882843268957241365 1780
UVM_INFO @ 390393838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_check_fail_vseq] wait timeout occurred! 1 test run
otp_ctrl_check_fail 11680854951107020198284634263558503457460835701537934284466314150038095440800 89
UVM_INFO @ 10002547016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 19392387907469208428777352265051610201034978428029477976892284036433725895680 7345
UVM_INFO @ 6571825870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 88841320098047262907209516382324935655416093726972597284483929522144878155233 9709
UVM_INFO @ 6801525893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 71110315825253103910923208031056016487297533411940178441687446053784387718696 2669
UVM_INFO @ 10876449154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---