Simulation Results: pwrmgr

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 97.57 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.75 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
95.62%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.860s 21.703us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.640s 56.285us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.850s 18.827us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.440s 989.403us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.050s 47.837us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.050s 80.631us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.850s 18.827us 5 5 100.00
pwrmgr_csr_aliasing 1.050s 47.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.230s 626.900us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.230s 626.900us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.040s 225.107us 10 10 100.00
pwrmgr_lowpower_invalid 0.850s 52.444us 10 10 100.00
reset 17 20 85.00
pwrmgr_reset 2.180s 1000.000us 9 10 90.00
pwrmgr_reset_invalid 1.050s 102.129us 8 10 80.00
main_power_glitch_reset 9 10 90.00
pwrmgr_reset 2.180s 1000.000us 9 10 90.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.270s 260.860us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.120s 246.002us 10 10 100.00
disable_rom_integrity_check 9 10 90.00
pwrmgr_disable_rom_integrity_check 1.020s 1000.000us 9 10 90.00
stress_all 8 10 80.00
pwrmgr_stress_all 7.260s 10345.598us 8 10 80.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.870s 21.902us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.200s 523.777us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.200s 523.777us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.640s 56.285us 1 1 100.00
pwrmgr_csr_rw 0.850s 18.827us 5 5 100.00
pwrmgr_csr_aliasing 1.050s 47.837us 1 1 100.00
pwrmgr_same_csr_outstanding 0.910s 96.009us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.640s 56.285us 1 1 100.00
pwrmgr_csr_rw 0.850s 18.827us 5 5 100.00
pwrmgr_csr_aliasing 1.050s 47.837us 1 1 100.00
pwrmgr_same_csr_outstanding 0.910s 96.009us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.590s 936.202us 25 25 100.00
pwrmgr_sec_cm 1.480s 708.680us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.480s 708.680us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.480s 708.680us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.590s 936.202us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.350s 838.918us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.270s 260.860us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.300s 910.473us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.110s 140.988us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.690s 31.145us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.480s 708.680us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.480s 708.680us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.480s 708.680us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.790s 58.471us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.860s 37.727us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.110s 163.857us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.850s 18.827us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.850s 18.827us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 4 10 40.00
pwrmgr_escalation_timeout 0.940s 189.310us 4 10 40.00
stress_all_with_rand_reset 10 10 100.00
pwrmgr_stress_all_with_rand_reset 10.000s 10084.240us 10 10 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 6 test runs
pwrmgr_escalation_timeout 67090000577294195953609040221255667712585769057251060689224627442387780267196 79
UVM_ERROR @ 99800832 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99800832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 110001135659518409282730633543212621982857953794400735689348852793638597162803 79
UVM_ERROR @ 102697550 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102697550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 99281411807534146311636746471778322471775786353195514362181491176752797039239 79
UVM_ERROR @ 98947854 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 98947854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 52384553877545081158078906804422549507102901137891886243887661251041399194196 79
UVM_ERROR @ 356465764 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 356465764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 36639131779285643480789660086913604562743639112446790506946789797745596925510 79
UVM_ERROR @ 119893419 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 119893419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 103189947113840387618748131677064696312686992403646929191287417094224714903887 79
UVM_ERROR @ 188719265 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 188719265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 2 test runs
pwrmgr_stress_all 92277910542686039070693747650713441399472731184599109243575419273439283209987 281
UVM_INFO @ 10647841074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 48867295383149581761125978445315501793619735412125086610553209124525463762925 285
UVM_INFO @ 10345598437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
pwrmgr_reset 35880966001648193468349560426505920811331093194823796803405705905340785101856 193
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 44297384237384638769027859322772759200406903022040997362070289976773161283555 112
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown 1 test run
pwrmgr_reset_invalid 3737350869816363625321908421628871021305382918244423880892973545190814400374 97
UVM_INFO @ 36250720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit 1 test run
pwrmgr_reset_invalid 52181417527073193612119620079839498864119713241187591952818169872684968213910 104
UVM_INFO @ 73035090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---