| V1 |
|
100.00% |
| V2 |
|
85.04% |
| V2S |
|
100.00% |
| V3 |
|
55.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.840s | 472.806us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 18.624us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.880s | 129.832us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.960s | 1053.542us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.230s | 74.982us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.190s | 25.495us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.880s | 129.832us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.230s | 74.982us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 20 | 5.00 | |||
| rv_timer_random_reset | 3.760s | 4486.683us | 1 | 20 | 5.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.660s | 1287.961us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 480.930s | 794589.008us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 480.930s | 794589.008us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 9.770s | 5556.539us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.790s | 14.263us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.900s | 15.356us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.960s | 621.896us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.960s | 621.896us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 18.624us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.880s | 129.832us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.230s | 74.982us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.190s | 43.526us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 18.624us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.880s | 129.832us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.230s | 74.982us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.190s | 43.526us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.280s | 69.491us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.770s | 229.364us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.770s | 229.364us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 5 | 10 | 50.00 | |||
| rv_timer_min | 1.660s | 211.106us | 5 | 10 | 50.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.500s | 176.224us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 17 | 20 | 85.00 | |||
| rv_timer_stress_all_with_rand_reset | 62.070s | 7201.473us | 17 | 20 | 85.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 24 test runs | |||
| rv_timer_random_reset | 99157131390662461614969241031293828996350400966540804468879030243657010666412 | 75 |
UVM_INFO @ 100059965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 70756355608114742685125874624174065435757287058880989642676787602418589217291 | 76 |
UVM_INFO @ 87959150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 32997569743161219736486614643301104007469964797866462936056450475567546450665 | 75 |
UVM_INFO @ 1068948443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 109080737457058625364688655811887275807937492062276433837792299549355693507543 | 75 |
UVM_INFO @ 404368190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 86771792747571849117434236082725168725990855053474481180165417536648369096828 | 75 |
UVM_INFO @ 247685823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 6470071077370442948935293803218168604594516191729129126692367663066745892084 | 76 |
UVM_INFO @ 277821513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 31600783728486753347611925993443508628092708664341299468345543505005767575901 | 77 |
UVM_INFO @ 1816762522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 36689391160742245453617701547051691156584799501330693066733798796211556389313 | 75 |
UVM_INFO @ 294416976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 47894391059567853234957986043678019632954149704235150408087427708106872842232 | 75 |
UVM_INFO @ 211106392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 88650030450542172959626540159902322574564250272131084220176675971144424300044 | 76 |
UVM_INFO @ 757622960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 66296959639515461630669915971275097380067301237733903818880711364395678781393 | 75 |
UVM_INFO @ 67156459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 88234580860020263623074892641226598552312518372501359794656869938476630414846 | 75 |
UVM_INFO @ 4486683175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 54740251991552361806764518651222049091706837760666758608394771711470955921951 | 75 |
UVM_INFO @ 156359466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 83167538312345478801360265928603097825987513461510824697784692275797726637650 | 75 |
UVM_INFO @ 291143438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 82058886812525616825876583028115658255967826716365687034432656716787671947127 | 76 |
UVM_INFO @ 148300882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 46326737808795773521834260536363248949263790026259333235667085241187119713934 | 75 |
UVM_INFO @ 78066889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 82827159445799216448756809682715116782177495168416860503223930420631802580432 | 75 |
UVM_INFO @ 133761480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 54170243850537124192978500606283566289126425499988097260814002908038602606399 | 75 |
UVM_INFO @ 373161503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 98670343411742092259773690196646459946804977505432267487484095223728896133727 | 75 |
UVM_INFO @ 506093865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 53883124129270339467067178491906598101843419991595219635036985937065224539617 | 75 |
UVM_INFO @ 79219477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 112717706612819036689329668149998801510072222420967858236806949213536302694374 | 75 |
UVM_INFO @ 56511671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 91774244224650080024796459059921865568672111103049893017269639646564803222430 | 75 |
UVM_INFO @ 242873892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 60953397718800421284281723247479120146441994852933429283014023202640917888069 | 75 |
UVM_INFO @ 127616798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 74068881671593382954673400766775515434138619471134034751290510653684672339478 | 75 |
UVM_INFO @ 858436401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 10 test runs | |||
| rv_timer_max | 65254948270769803280984146224201537894006876119399116579928539775711903088421 | 75 |
UVM_INFO @ 44434077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 7153424177489576699872667332103136789461503318545902169539082001508689641107 | 75 |
UVM_INFO @ 46838016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 99375474406067875220948849206696163738429745232005491423257673827379054436866 | 75 |
UVM_INFO @ 90487233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 95938983783995412019491322288808387693651474640822422464176667583877840331933 | 76 |
UVM_INFO @ 97722139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 112989726644949839063007156236645848883058351765756176794721159182480308241717 | 76 |
UVM_INFO @ 96351950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 36088745455833540573469925266100091887306768652422522684284383889141050596170 | 75 |
UVM_INFO @ 72583374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 58170035402550217361223385751087948208107317310829658272461520577054120668373 | 75 |
UVM_INFO @ 176223846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 15388975443673529902901426098711020895251365771414838204332651622938581321072 | 75 |
UVM_INFO @ 42613634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 51263596841813421803364939987681720020334888658595604020574553016672995898097 | 76 |
UVM_INFO @ 176500203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 87315225463151592960740818912004774332446534296215286619610945615673762439886 | 75 |
UVM_INFO @ 133351758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 57561063534717101050559414595266793251102580281739823516406832600514523152155 | 378 |
UVM_INFO @ 6072078965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 90961953272542527527873778037980586582724798297199035535283245682830109704017 | 323 |
UVM_INFO @ 35526746532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| rv_timer_stress_all_with_rand_reset | 112261296060302605229573421924535670597909325628357767943719272015930629802912 | 199 |
UVM_INFO @ 3128500319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|