Simulation Results: spi_host

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.44 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 90.000s 9199.019us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.589us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 16.634us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 274.983us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 16.485us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 90.024us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 16.634us 5 5 100.00
spi_host_csr_aliasing 2.000s 16.485us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.914us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 6.000s 62.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 67.799us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 36.000s 2403.487us 10 10 100.00
spi_host_error_cmd 2.000s 25.247us 10 10 100.00
spi_host_event 35.000s 2972.443us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 5.000s 101.503us 10 10 100.00
speed 10 10 100.00
spi_host_speed 5.000s 101.503us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 5.000s 101.503us 10 10 100.00
upper_range_clkdiv 3 5 60.00
spi_host_upper_range_clkdiv 235.000s 200000.000us 3 5 60.00
sw_reset 10 10 100.00
spi_host_sw_reset 29.000s 809.713us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 24.846us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 5.000s 101.503us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 5.000s 101.503us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 90.000s 9199.019us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 90.000s 9199.019us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 64.000s 7553.314us 10 10 100.00
spien 10 10 100.00
spi_host_spien 10.000s 519.537us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 628.000s 138497.460us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 9.000s 2829.829us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 36.000s 2403.487us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 38.063us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 20.663us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 49.970us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 49.970us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 17.589us 1 1 100.00
spi_host_csr_rw 2.000s 16.634us 5 5 100.00
spi_host_csr_aliasing 2.000s 16.485us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 100.773us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 17.589us 1 1 100.00
spi_host_csr_rw 2.000s 16.634us 5 5 100.00
spi_host_csr_aliasing 2.000s 16.485us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 100.773us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 343.839us 25 25 100.00
spi_host_sec_cm 7.000s 314.245us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 343.839us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
spi_host_upper_range_clkdiv 61837908433391368069575631524285413700608615890886231461555925442551059373475 129
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_upper_range_clkdiv 73117300946877450027600912590499293273827759718123533523573643507463634438525 129
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---