Simulation Results: sram_ctrl/main

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.83 %
  • code
  • 95.81 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.23 %
  • line
  • 96.90 %
  • branch
  • 94.48 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 6.000s 1374.711us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 75.682us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 21.744us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 35.600us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.926us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 373.010us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 21.744us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 15.926us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 296.000s 92628.796us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 129.000s 18438.954us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 48.000s 13864.368us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 226.000s 22343.416us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 198.000s 17688.185us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 88.000s 130015.483us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 65.000s 15749.627us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 37.000s 24617.150us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 7.000s 675.785us 8 8 100.00
sram_ctrl_partial_access_b2b 333.000s 161418.126us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 9.000s 2748.177us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 2641.913us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 668.791us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 15.000s 4501.787us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 4.000s 3746.084us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 483.000s 355327.686us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 18.665us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 250.010us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 250.010us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 75.682us 1 1 100.00
sram_ctrl_csr_rw 2.000s 21.744us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 15.926us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 33.811us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 75.682us 1 1 100.00
sram_ctrl_csr_rw 2.000s 21.744us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 15.926us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 33.811us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 70.000s 140499.691us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 374.006us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 2744.488us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 374.006us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 2744.488us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 4501.787us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 4501.787us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 21.744us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 37.000s 24617.150us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 37.000s 24617.150us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 37.000s 24617.150us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 65.000s 15749.627us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 1363.113us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 70.000s 140499.691us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 7.000s 700.243us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 6.000s 1374.711us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 6.000s 1374.711us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 37.000s 24617.150us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 374.006us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 65.000s 15749.627us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 374.006us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 374.006us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 6.000s 1374.711us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 374.006us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 31.000s 18000.809us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 11338115415692678642488106118953922681028944760563922791912874688318539216741 86
UVM_INFO @ 1355783310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 106056894197972826596808410519566250263028446210800391761126277496820393029865 86
UVM_INFO @ 2641913099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 5240533079457972687169236666656695479704779929527185819034171854887593597488 86
UVM_INFO @ 1349523228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 82289742513484409360600086792481560476287874585456547544382148171276962252822 86
UVM_INFO @ 1321047865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 111953918167814431126201649214368111178262056762051924739019851307649709313831 86
UVM_INFO @ 4137099520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 106164799083969558483704645391879833870394806085154195362800803429840713903162 86
UVM_INFO @ 680840853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 68948784267030495695129070965714850617501930495212906570499821650192601445354 86
UVM_INFO @ 2748176607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 96631577847866221412738233577776497252511785379469769307110028129142667329464 86
UVM_INFO @ 660342122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 69738147296997521606055400915280351684441750979458959487646167739588919925665 86
UVM_INFO @ 1340872744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 31826727385780992260112172969290521538263158203107088701068327168431147678687 86
UVM_INFO @ 1834754541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 21230392104444556664984872154540263100888296056519765869561932471839654780381 86
UVM_INFO @ 3000583249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 31897452553880870301416241179200459441260465303991027557533726378607257006921 86
UVM_INFO @ 5573088586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 1234823983795998918861165724341196092680649066965856490419009471871707814614 86
UVM_INFO @ 1783970967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 54722900910232216020074661335965349558514514159968757440269052808995768503814 86
UVM_INFO @ 688367739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 53570059900811327899153342776253711840184018172640517193414374095953381141573 86
UVM_INFO @ 680748111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 93893864483385175910203215358971876466513996976130662958849332167088586382129 86
UVM_INFO @ 2752546568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 99036609328239225548291423806469361097334454916844418627938018754532818147634 86
UVM_INFO @ 685834759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 108945394468630925976573419274104833386085951707299528698414510082694347996209 86
UVM_INFO @ 1344453655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 92727755890949581593634061902729454178140691139135604015693819842864293910804 86
UVM_INFO @ 688953974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 6469244200931778014430667933558730265844999695234828424430322770093568839629 86
UVM_INFO @ 668791075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 29391911505474304551803543879114082729485112896840794349089109384243868334053 86
UVM_INFO @ 2664298117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 73989193359385027701003989735615898774013271732934474939836799658831321231519 86
UVM_INFO @ 677511699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 108811343462056588302969668408867374363556197656415053913148056178803474965011 86
UVM_INFO @ 694668956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 35704240621406651094011363865658786657293217316068617711106607976171355585493 86
UVM_INFO @ 674188261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---