Simulation Results: sram_ctrl/ret

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.78 %
  • code
  • 83.45 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 93.95 %
  • line
  • 95.06 %
  • branch
  • 89.80 %
  • toggle
  • 82.29 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
87.50%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 2.000s 75.221us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 22.037us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.945us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 378.881us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.344us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 150.793us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 14.945us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 14.344us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 13.000s 3204.221us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 6.000s 698.727us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 8.000s 1548.196us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 238.000s 3871.959us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 9.000s 994.994us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 26.000s 994.954us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 9.000s 1611.232us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 20.000s 3628.164us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 253.239us 8 8 100.00
sram_ctrl_partial_access_b2b 330.000s 24764.477us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 107.957us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 44.872us 0 8 0.00
sram_ctrl_throughput_w_readback 3.000s 498.218us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 13.000s 530.779us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 45.030us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 65.000s 65798.640us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 25.228us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 325.753us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 325.753us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 22.037us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.945us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 14.344us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 69.655us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 22.037us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.945us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 14.344us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 69.655us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1956.772us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 1053.512us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 4505.432us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1053.512us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 4505.432us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 530.779us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 530.779us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.945us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 20.000s 3628.164us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 20.000s 3628.164us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 20.000s 3628.164us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 9.000s 1611.232us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 74.772us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1956.772us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 69.813us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 75.221us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 75.221us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 20.000s 3628.164us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1053.512us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 9.000s 1611.232us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1053.512us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1053.512us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 2.000s 75.221us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1053.512us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 8 87.50
sram_ctrl_stress_all_with_rand_reset 59.000s 1353.902us 7 8 87.50

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 68582873136853034366560654606480990809149392683163387725383202100176241250061 86
UVM_INFO @ 107956638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 74857496483282127218967525329157080821028312198539425150707795214506510710171 86
UVM_INFO @ 44871624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 108678758871104259653954114761521879161612221133882030575074260724637454479025 86
UVM_INFO @ 110797660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 43061876879209020139896824906632657829784512500669790961262136785465643517942 86
UVM_INFO @ 36667214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 71663495500579919207194672082134079173552543718203293274476857996271656543145 86
UVM_INFO @ 271933866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 65051573857608679791553222697234976260415485150449723478522065946632587034361 86
UVM_INFO @ 54226164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 25992080256610524523435574570215725962740478338766204412392502671858235252950 86
UVM_INFO @ 33268341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 43076505283709011081895965234596017328002858982012413431704702849161836594816 86
UVM_INFO @ 60890332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 53892816350730064260262316869448772105311290941344401116362330943532733251367 86
UVM_INFO @ 31680339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 56393945308399113687632444916736690243772142946013279292978428895442942807630 86
UVM_INFO @ 94338542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 60254567303518125011609003056086691294157494812617679684193923303233722097524 86
UVM_INFO @ 24871975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 47667227463550828856929719603881089224856513248129911194462744661605693866636 86
UVM_INFO @ 27613831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 26697253154105764795122307206621725334285340777728246825696619045976715194434 86
UVM_INFO @ 99044531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 94027729100109041101330895228014457052741498374235471306291855593971075848478 86
UVM_INFO @ 197367613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 19486995408975795917505864384589566145443225571868751461763129524599123119721 86
UVM_INFO @ 26374080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 174759451735312306665439729013343690019571165432653036691917216632003225555 86
UVM_INFO @ 116680267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 57204058675664349951248608341509137036750900808075553122376437566780537917931 86
UVM_INFO @ 59524581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 75865114991905703940523227699121468178495836703452794072828867577177280605401 86
UVM_INFO @ 62975381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 15552028457644316451042829756184011273773112245357041859220330810431890610869 86
UVM_INFO @ 115023592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 70125005320362239443788003683234312943456233827819961332901057508712206705377 86
UVM_INFO @ 58978112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 19395246369611328365906655044657274527420133616178243198626261640580152353871 86
UVM_INFO @ 567664396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 12617678783521817229316283348591136263844581255049033021278802417783001272310 86
UVM_INFO @ 498218327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 111340198649721902127794330820777447851204127247937911020768779041856574858227 86
UVM_INFO @ 35483004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 29209831227414820730214769605848367540896174066929712791925815081750298705453 86
UVM_INFO @ 30237398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 114930670817046379424992243759322024246911990063067639429423054216486576971040 97
UVM_INFO @ 31258644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---