Simulation Results: uart

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.33 %
  • code
  • 96.86 %
  • assert
  • 98.85 %
  • func
  • 99.30 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.23%
V2S
100.00%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 14.930s 5864.227us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.920s 30.776us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.980s 30.744us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.630s 325.573us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.930s 56.699us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.240s 318.904us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.980s 30.744us 5 5 100.00
uart_csr_aliasing 0.930s 56.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 114.600s 88074.335us 10 10 100.00
parity 20 20 100.00
uart_smoke 14.930s 5864.227us 10 10 100.00
uart_tx_rx 114.600s 88074.335us 10 10 100.00
parity_error 20 20 100.00
uart_intr 115.300s 63762.556us 10 10 100.00
uart_rx_parity_err 103.210s 205952.360us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 114.600s 88074.335us 10 10 100.00
uart_intr 115.300s 63762.556us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 182.330s 160163.595us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 202.370s 141789.058us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 297.800s 189172.622us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 115.300s 63762.556us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 115.300s 63762.556us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 115.300s 63762.556us 10 10 100.00
perf 10 10 100.00
uart_perf 565.230s 18875.280us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 13.790s 8254.484us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 13.790s 8254.484us 10 10 100.00
rx_noise_filter 2 10 20.00
uart_noise_filter 49.300s 59714.873us 2 10 20.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 23.890s 47424.932us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 7.850s 7061.575us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 23.140s 7873.523us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 602.680s 95841.077us 10 10 100.00
stress_all 7 10 70.00
uart_stress_all 475.510s 244544.435us 7 10 70.00
alert_test 10 10 100.00
uart_alert_test 0.920s 41.492us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.970s 38.449us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 3.280s 633.440us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 3.280s 633.440us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.920s 30.776us 1 1 100.00
uart_csr_rw 0.980s 30.744us 5 5 100.00
uart_csr_aliasing 0.930s 56.699us 1 1 100.00
uart_same_csr_outstanding 1.060s 57.302us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.920s 30.776us 1 1 100.00
uart_csr_rw 0.980s 30.744us 5 5 100.00
uart_csr_aliasing 0.930s 56.699us 1 1 100.00
uart_same_csr_outstanding 1.060s 57.302us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.280s 572.943us 5 5 100.00
uart_tl_intg_err 1.780s 185.976us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.780s 185.976us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
uart_stress_all_with_rand_reset 54.780s 4490.656us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 8 test runs
uart_stress_all 37329727538019001669779196455949955773532082773397665508393709930471836796374 75
UVM_ERROR @ 767225377 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 822811505 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 875418332 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 926468500 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
uart_noise_filter 91317060342641658164290467744628448635455459179713254533733143228671301858327 81
UVM_ERROR @ 59074325853 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 59074409187 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 59074575855 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (58 [0x3a] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 59075159193 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
uart_stress_all_with_rand_reset 115082367185823824580210694457754246696452083600028457639775410779905890728117 105
UVM_ERROR @ 1730955908 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 1777335908 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/718
UVM_INFO @ 1850375908 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 11/718
UVM_INFO @ 1938713865 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
uart_stress_all 74265745544379610804334255296706613894164216871757080693131364226546125166802 96
UVM_ERROR @ 191854193641 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 191868273641 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 191868553641 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 191880593641 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 104004271180701828739587565857301178442180687341085722665351165350633068290418 80
UVM_ERROR @ 35328346731 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 35409626731 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 35409626731 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 35448106731 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
uart_noise_filter 103426731621817760358253109813840697391218265301375312840739048763894341818725 76
UVM_ERROR @ 2233941192 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2278359280 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 2278359280 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2288703361 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (133 [0x85] vs 248 [0xf8]) reg name: uart_reg_block.rdata
uart_stress_all 88043976848247883387775605552309428000351519791606288554993757189337377002624 83
UVM_ERROR @ 67967667854 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 69124952411 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 69126095267 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 69126761933 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 103276481047150050689594072321453234136347097034898146299015729429907743331414 123
UVM_ERROR @ 6656891167 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 6817392772 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/321
UVM_ERROR @ 7046076877 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 8
UVM_ERROR @ 7046167787 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 3 test runs
uart_noise_filter 91623393482887069201815212856881895610779315670990166551571115795030221734949 74
UVM_ERROR @ 527696938 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 531503382 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 531503382 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 540051752 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
uart_noise_filter 105696901637255911857867563799678764071865096000194597655727353114744010064355 74
UVM_ERROR @ 103683731 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 111051931 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 111051931 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 115114967 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
uart_stress_all_with_rand_reset 93667142451789198359675643682267236665319154521876704354453677931574542042524 137
UVM_ERROR @ 1765112906 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1765112906 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 1810092659 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/61
UVM_INFO @ 1912799627 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/61
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 3 test runs
uart_noise_filter 415958598724135308086020967022477949524304162294396593862238779072277521701 74
UVM_ERROR @ 376327581 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 376367581 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 407967581 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 407967581 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
uart_noise_filter 44250034334514728224036110193347856285897929999161707803987600762902652056064 75
UVM_ERROR @ 11160912129 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 11160932537 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (162 [0xa2] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 11464317865 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 11464317865 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 112458363879809957862494607929954157513200631961748249880826957085447088017681 76
UVM_ERROR @ 3949959787 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3950012417 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (175 [0xaf] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3998895161 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 3998916213 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty