Simulation Results

Simulation Results: adc_ctrl

08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.33 %

code
95.61 %

assert
92.71 %

func
13.66 %

line
98.86 %

branch
97.40 %

cond
87.43 %

toggle
99.76 %

FSM
94.59 %

Validation stages

V1		100.00%
V2		49.72%
V2S		100.00%
V3		10.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	12.460s	5884.504us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.840s	989.231us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	2.260s	486.702us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	5.560s	6244.813us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	5.180s	1025.697us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.670s	414.458us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	2.260s	486.702us	5	5	100.00
	adc_ctrl_csr_aliasing	5.180s	1025.697us	1	1	100.00

88/177 passed

49.72 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.110s	498.726us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.200s	482.529us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.260s	478.399us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.070s	449.282us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	2.210s	522.745us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.010s	390.012us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	1.900s	430.950us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.160s	507.167us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	10.410s	5576.661us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	89.120s	37581.163us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	187.580s	81231.269us	10	10	100.00
stress_all				1	10	10.00
	adc_ctrl_stress_all	208.640s	124440.313us	1	10	10.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	1.700s	417.955us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.020s	422.547us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	4.150s	495.543us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	4.150s	495.543us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.840s	989.231us	1	1	100.00
	adc_ctrl_csr_rw	2.260s	486.702us	5	5	100.00
	adc_ctrl_csr_aliasing	5.180s	1025.697us	1	1	100.00
	adc_ctrl_same_csr_outstanding	19.920s	5128.328us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.840s	989.231us	1	1	100.00
	adc_ctrl_csr_rw	2.260s	486.702us	5	5	100.00
	adc_ctrl_csr_aliasing	5.180s	1025.697us	1	1	100.00
	adc_ctrl_same_csr_outstanding	19.920s	5128.328us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	8.180s	7589.900us	5	5	100.00
	adc_ctrl_tl_intg_err	23.410s	8836.610us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	23.410s	8836.610us	25	25	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	adc_ctrl_stress_all_with_rand_reset	17.170s	9381.850us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				98 test runs
	adc_ctrl_filters_polled	91746018863399292450346904713323910367006914091363779814504059620281678672176	386	UVM_INFO @ 312323620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	1591573194615480719867802108817872016267983968840529118567381820631641064630	386	UVM_INFO @ 487597069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	102833490038845518006282442695570510964902846892611132825710027145135233075164	386	UVM_INFO @ 403346823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	90632678539016058991202745609503895438277091590038671379022623360244290623807	386	UVM_INFO @ 343238118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	32227479911499976749919894490932372068081909520864655985049363368216728359009	386	UVM_INFO @ 366462881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	60568642307802533418231813001792689434680568272942044936568023502970515299321	386	UVM_INFO @ 408528710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	63137288196213272248576542214658230635218394683036003185521147111624936920494	386	UVM_INFO @ 351735976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	9891833782930661532914015589292724437295207315020540253422444214304307863201	386	UVM_INFO @ 403211804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	57607650463977445030075779028615838491453875922243069570191229124307424759213	399	UVM_INFO @ 992338499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	64664925268097385073379223924677360974078177293858487861159484183378492005406	426	UVM_INFO @ 124440312559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	111255341862854111331364995198116825704385650192503885801275335504181137981928	386	UVM_INFO @ 303957318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	39624661345352836675208634462926208272941463084127255593424714452077955175392	386	UVM_INFO @ 417585387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	80081108985612852540142282153340628988921582477697696389001259258318042261364	386	UVM_INFO @ 375057283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	13128525390643133939708728347811950991904356940498309799552384338326300264127	386	UVM_INFO @ 344146678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	58931170542601792826746004422995224587286471061696390328770364115710418838698	386	UVM_INFO @ 462639202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	30822633582540142012965594711334149218348396338870529523624120133965490669887	386	UVM_INFO @ 390011930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	80143090021573802518237835964401600486944617554378027281652326613668424414291	386	UVM_INFO @ 430376768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	28737142287534173690952067737493432712047870262825309672333460213487722191159	386	UVM_INFO @ 430949739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	27770250413369421694650961962153773179239657733087041594783625663458623117682	413	UVM_INFO @ 1072925304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	70851979278577922659955733843731310619106881260871044313384691559933550111574	387	UVM_INFO @ 550884941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	114195570723149696426147178647944009551399591524103608846161231597114025812646	386	UVM_INFO @ 498726238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	86411507658924327984084177518772782446736767184821758629169126981602674251026	386	UVM_INFO @ 308804192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	83055588374729848865780632918057868488212598241606773248606973784254587965976	386	UVM_INFO @ 345313439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	77619361961927154092134953683701284389109115885094402876958429807424886523691	386	UVM_INFO @ 457630572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	56729190017390424750370092400764976506329946609179424276663364507098764104268	386	UVM_INFO @ 412465277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	65163324116721296845080059053731725531753052385736688577541411407928106150103	386	UVM_INFO @ 330269285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	84527339712664920786361739058449910370490350282694979653154967248645112809896	386	UVM_INFO @ 357176559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	20021786376637123546885178891821358008912158759091562792701591962418001419385	386	UVM_INFO @ 276674658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	43094765691936645606394539209793351017621412880534563168802274652513104085628	386	UVM_INFO @ 296393976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	113461150556893583134570363408494535818424032961545021711437813378728744370241	386	UVM_INFO @ 327962144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	42876853906383752594258069812698243059969225551887125157805890602187397945665	386	UVM_INFO @ 399982993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	50420157825472640358145883123419273870644235267633097715973398438729303000688	386	UVM_INFO @ 354370092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	33586957631642760994885969143778212265211122219295640032592379678431151666171	386	UVM_INFO @ 522744629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	61429894444668937293316746632865257189364839956376788363638053203304454093792	386	UVM_INFO @ 526631333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	110573006818311295614053606892896381832641863278118093855300851175960653392995	386	UVM_INFO @ 469436335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	6953459431482221227615653011379661537327276034995679814905217331923192289669	386	UVM_INFO @ 337696853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	5025721200873318204294599480145750089555954617514043751705399421211617848457	406	UVM_INFO @ 1050002535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	21547079520738110766600010254200546741973347486211845386902073215718228332427	387	UVM_INFO @ 600585270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	115763566157907385867034867225400976826663875281743137774853671039458435953299	386	UVM_INFO @ 473486027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	76846992480424586293253866328746156167677453718184147962091212479337339159009	386	UVM_INFO @ 304149002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	42776276820497407507328155228539336655128849063286277761274364372801248934200	386	UVM_INFO @ 460055086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	111728650918478194392528601000090494998218470904438138191280011768350463651788	386	UVM_INFO @ 349726419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	84658465782144860817104144042894730036408902107998347249011858371934629901163	386	UVM_INFO @ 425469047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	87223521902189891226859731709302859281263115193612541919567826967237308418793	386	UVM_INFO @ 375695406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	73329832603817131405618103262700292448417251192463537218943739900390814313446	386	UVM_INFO @ 473007763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	65990081534837271760685303222812580837091348727075853386881419208399551960949	386	UVM_INFO @ 444341485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	100738082728206713508024352304797576495884367964684870102209528070604918799491	392	UVM_INFO @ 781003401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	67299335702900475834517807429956816731873077192039052281023287847045512571022	387	UVM_INFO @ 766744990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	76154130646403655752728098847737258856748413388499936578311137610316885155967	386	UVM_INFO @ 351234363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	28982793143572857771125095053059711068490900266689474639301683717646285769300	386	UVM_INFO @ 516870651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	20476431396173363178007368898740796475043572393734681170843020524087462221793	386	UVM_INFO @ 473039313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	103934529999167578866517502542851311169189191314879693379663072778616720341381	386	UVM_INFO @ 449281955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	75605757324850465561717430399851336649372669579939128238801928664491965383625	386	UVM_INFO @ 525264947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	75176909354958423290922410658260448017974914542032500428841264306154105668943	386	UVM_INFO @ 433574658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	1335215586083159546597742208465340781217408193307734235647498191653632178401	386	UVM_INFO @ 439162839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	71340937320301823162049332945644441287759593529739251493356600001121681924659	386	UVM_INFO @ 520960638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	59677601405058008964494866870673772390925745727886400516056429130809517030940	420	UVM_INFO @ 6054255585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	4949399860680300871122911161523417087979308383891193931887112382555129643314	387	UVM_INFO @ 701211174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	61949012660001522592903945654121331420001719476935126623948935334657300376889	386	UVM_INFO @ 293041631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	28184414531190491552746093497909927687721632037719974755136292104627169077380	386	UVM_INFO @ 360371311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	40854061545788335970140633569413041079817583187744291285879043949567380766815	386	UVM_INFO @ 502768064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	7243152972862231457445882446684613277487329442176857981541894982478645437786	386	UVM_INFO @ 474631349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	41567161457296507621154186451505893192914548204745736052295089368915224742740	386	UVM_INFO @ 391763440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	63868362859398200095299955908876725483621163929295820359379298563873886387756	386	UVM_INFO @ 277431065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	27071893579729629939333526079434277947169234441439899200639761960295384929309	386	UVM_INFO @ 516045042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	8356678119077965630565064403275361190400002332196886850790934779499923433595	386	UVM_INFO @ 340769819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	56299673237640460868420458556745800332891702076956579082049524483601170382820	406	UVM_INFO @ 1069990753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	24353014312489636618486363324487773827555461961799892532842337484921720984550	387	UVM_INFO @ 694763830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	27635280852251634834755542974632592754382524441213885780519409058478636006867	386	UVM_INFO @ 282367505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	108268748595821307577410502418546771993986563637341188096643769719179615280634	386	UVM_INFO @ 482529129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	28090530635013147191198169190209983741292273678808255757483332687506523660396	386	UVM_INFO @ 478398934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	28068466203056866702561355860900182441514064165175128418412883866929031679581	386	UVM_INFO @ 499208077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	103905538566943121257045607172844069648497597196042700972624664783350246744383	386	UVM_INFO @ 417651193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	30480267315414831327551729962397624060027026052408774829004536362153498508878	386	UVM_INFO @ 391851070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	33445813456244803648875400762881550408334866822209720730314481194468555708533	386	UVM_INFO @ 507166705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	88743114751805229465548910277522062551364988154747799512408178084351603675020	386	UVM_INFO @ 331215698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	15211112517430272337196045483539742437846438440906817395266889392487463295009	406	UVM_INFO @ 999194154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	112835916497640634980264500791906401023096603384639950530114008747519671764256	536	UVM_INFO @ 124610073121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	88683841723169892355062165081186353390974072228393639876947530037210011044427	386	UVM_INFO @ 464248511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	43916442261342217598405907319339154169092108843970607202505439127633143823515	386	UVM_INFO @ 504177361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	81207110975527219808914199545102128323449316556256940816653027745401090949518	386	UVM_INFO @ 442514681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	54820550677784748801986989701383460336996399398947913378019092273477571555898	386	UVM_INFO @ 465168510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	37348948087422490451743538789847225365627744431505830674841433694683832387617	386	UVM_INFO @ 278491171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	82562653819958406621521612844494095321995848465697798728483862654137390675276	386	UVM_INFO @ 385842692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	1006345197844184230975545468552640087251706776969584475077857672068546864106	386	UVM_INFO @ 468606561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	38800839725285353685206346225935502347463700694696447995148333384151455967871	386	UVM_INFO @ 280656778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	103978786743979182228950809145274421488090256932377591731167998190579101418029	434	UVM_INFO @ 1709998151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	50457960288727385848888885841892396508080101983850925293313846725008130628653	539	UVM_INFO @ 114241908045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	49775042453826025966622169571245061663150692297504202140645846650993273175779	386	UVM_INFO @ 282116186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	76008393305452553425758776122724487153161610981641567987750299123646865968738	386	UVM_INFO @ 384123902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	110352575067372417512997584585963760299508083678877439686184866077687975869583	386	UVM_INFO @ 383602975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	42824665424245063556866180636140944785988846348369912299637663491036639042859	386	UVM_INFO @ 511102363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	50773766708332535027803799279422860667828486604204995418586556408879457746144	386	UVM_INFO @ 426705742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	12010787988562456687984527203932281672388994796422919435478223400928786984693	386	UVM_INFO @ 412948137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	37757880411652799653305837121658785547047409010061105109300040861851473737592	386	UVM_INFO @ 383060478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	99727920697965194622243876011966240007418318826570481139829499543275337777032	386	UVM_INFO @ 509775042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	43698075207776802230182758483211345577891848905425365268549874112528943532450	431	UVM_INFO @ 3255992116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	45871593573738093402613252440004691715881428297903186587139206693045244881817	387	UVM_INFO @ 733626417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---