| V1 |
|
100.00% |
| V2 |
|
89.15% |
| V2S |
|
99.02% |
| V3 |
|
10.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 78.790s | 2969.236us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.570s | 140.069us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 13.000s | 523.746us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 295.780s | 5775.844us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 146.480s | 3704.039us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 9.950s | 522.459us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 13.000s | 523.746us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 146.480s | 3704.039us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 352.010s | 12305.576us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 90.510s | 1503.029us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3349.980s | 75903.242us | 25 | 25 | 100.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 79.180s | 4703.780us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 78.790s | 2969.236us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 71.360s | 2694.218us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 72.910s | 4623.157us | 50 | 50 | 100.00 | |
| ping_timeout | 17 | 50 | 34.00 | |||
| alert_handler_ping_timeout | 440.040s | 39040.369us | 17 | 50 | 34.00 | |
| lpg | 98 | 100 | 98.00 | |||
| alert_handler_lpg | 3600.127s | 0.000us | 48 | 50 | 96.00 | |
| alert_handler_lpg_stub_clk | 3349.640s | 785202.742us | 50 | 50 | 100.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 4622.610s | 175845.630us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 1 | 20 | 5.00 | |||
| alert_handler_entropy_stress | 21.260s | 5110.880us | 1 | 20 | 5.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 6.130s | 379.741us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.660s | 13.901us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 25.510s | 1195.466us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 25.510s | 1195.466us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.570s | 140.069us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.000s | 523.746us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 146.480s | 3704.039us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 20.830s | 355.801us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.570s | 140.069us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.000s | 523.746us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 146.480s | 3704.039us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 20.830s | 355.801us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 398.510s | 5684.436us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 398.510s | 5684.436us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 398.510s | 5684.436us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 398.510s | 5684.436us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1191.760s | 18606.673us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 93.760s | 5045.964us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 93.760s | 5045.964us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 398.510s | 5684.436us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 78.790s | 2969.236us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 78.790s | 2969.236us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 78.790s | 2969.236us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 78.790s | 2969.236us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 79.180s | 4703.780us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 48 | 50 | 96.00 | |||
| alert_handler_lpg | 3600.127s | 0.000us | 48 | 50 | 96.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 79.180s | 4703.780us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3349.980s | 75903.242us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3349.980s | 75903.242us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 23.580s | 824.849us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 10 | 10.00 | |||
| alert_handler_stress_all_with_rand_reset | 242.320s | 6900.714us | 1 | 10 | 10.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 32 test runs | |||
| alert_handler_ping_timeout | 31852308190604396044300871754313553411144255537011264649473757847194484151125 | 96 |
UVM_INFO @ 2102517706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 47519634680480599505919474013957046137602175664319076110177956016796030223533 | 87 |
UVM_INFO @ 13576714162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45341749741087794514067613051643970786552190620039358670939446439211342487380 | 114 |
UVM_INFO @ 6422281694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 40557065952444194627027351006374867018262567296859866864081352232175321960837 | 97 |
UVM_INFO @ 30714624935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 115534395764077704240482764439285182385014253848893947731885797044643329825084 | 108 |
UVM_INFO @ 20993683753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 6981589470176154040502007428466874679860829471730931805034329888294916521062 | 93 |
UVM_INFO @ 2760978037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 38578691563825929998667388102757796231332293292006570001048300698969697313716 | 114 |
UVM_INFO @ 14642635257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 34480067716315674605572048367819983466010203130954106035540304836054760828311 | 141 |
UVM_INFO @ 23734273683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 96157106261300194129845670009645060985995119214386583689836726441057862800464 | 93 |
UVM_INFO @ 10036636072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 105331469731059006300667442664329555800176866051832424197781148358582330622469 | 90 |
UVM_INFO @ 4224434237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 4868770517359683316927990303087325438792540130327408243408018095626188784544 | 84 |
UVM_INFO @ 2950430691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 90299548909983559242280829106016156607562669859877124560782640105846198679275 | 80 |
UVM_INFO @ 17285341748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16328781288562450372546817935609593790595584861507119528125789332209695338327 | 121 |
UVM_INFO @ 73865924513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 88971248987297810103900064503331851150808568182281332266873335996574778715262 | 87 |
UVM_INFO @ 11167049263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 72609846178070379646445885385230662460829721977677704789645385122249718267353 | 87 |
UVM_INFO @ 1119339918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 1144465576518597155729190977955441240417359493370198348345375794711993106949 | 111 |
UVM_INFO @ 20940553479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 61264875354296145438075433697225030242157395477425342160105979055666605139478 | 108 |
UVM_INFO @ 32960789857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 39016790098252062581644661680529011787689355680398175007256495570875919122926 | 87 |
UVM_INFO @ 5179493171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 41556927369044145417134629284567893582833592546546952799386377547658882670005 | 147 |
UVM_INFO @ 46032253855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 71461557619948387310792461843091696397430345420717138261566073757674882778402 | 90 |
UVM_INFO @ 12561560232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 94023710213568261605116075528120563271091785568044400404085455697242894713626 | 99 |
UVM_INFO @ 9314861652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78685597112093331855016937351333213934635386203369526304241342349850911451543 | 99 |
UVM_INFO @ 1985148186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 106971873659003787328610924582799853658471909877983977209134223368879486931146 | 129 |
UVM_INFO @ 6427200121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 37587100538628721224716343863646955211315069291586082471037859054119294028509 | 118 |
UVM_INFO @ 24571604196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 47227491397943857540414220879700905578864193830381528084477193827880053484909 | 105 |
UVM_INFO @ 2845235363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53736236041515814654591631972230363779544269393995356843813144963189044171202 | 96 |
UVM_INFO @ 1734893122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 83782992261076854564524871552767268470325617680084726398051980377058127126296 | 147 |
UVM_INFO @ 32034524669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80542155966154802240590347817787502137966843982512289744511907678797892306423 | 90 |
UVM_INFO @ 9254781206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 9818771091424523941241940737851121744936866495804149731733010548604772769164 | 99 |
UVM_INFO @ 17210704675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 25198211306066547232232389933880175406909959298480817473753076191051927120078 | 117 |
UVM_INFO @ 41896816642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 55928231669439887845376965401265909495063069669525700815236377333736674219643 | 106 |
UVM_INFO @ 12031762578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 89081400458704807814398445164093745558950672916091622574387949392666394999861 | 96 |
UVM_INFO @ 5505301997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 19 test runs | |||
| alert_handler_entropy_stress | 86597479518997444701988476710621346552433595130285595245254494192812018358596 | 166 |
UVM_INFO @ 1527792785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 46312155534975295662184668873770209936473485015329255630362321980091285315692 | 206 |
UVM_INFO @ 5110879584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 20918187752017391382656958296299450043037969080410775800049923151736909835088 | 170 |
UVM_INFO @ 236994820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 111413272028690303369069571143671015061287531507203784496799468113799182841760 | 184 |
UVM_INFO @ 257443230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 76008543155728184145408883391869457449119642357893714678795001907388713086821 | 168 |
UVM_INFO @ 1314398940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 48122202506051196512331413298382697090771812748590502015214623113090407739376 | 204 |
UVM_INFO @ 332392241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 42478332639460873180118914028277858524990953156552304699043388099293616020032 | 212 |
UVM_INFO @ 2450930492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 4978733749967676339611612323070497930357710931567119897666864907919326442234 | 174 |
UVM_INFO @ 228496004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 21725221110438441776913093156232876965654052271192105844068144739198457783955 | 208 |
UVM_INFO @ 271050214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 105092056852185458188071283974359117077836480179129388917540557145447510821287 | 194 |
UVM_INFO @ 136663203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 84195526169277520679237679326581467701144378723852795895254867727600872773699 | 192 |
UVM_INFO @ 372077606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 110023728269127467900422339982920759152328383779156228918261394674426719394658 | 184 |
UVM_INFO @ 734881654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 3881107226782277587103140475142757398675677472018602013233210779662315628944 | 206 |
UVM_INFO @ 227990272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 109189757197379991887024672734648427988125972339071897340507650507347648785111 | 202 |
UVM_INFO @ 257846455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 95401653781885631081781790007179734804531828761660404042381472995992855468289 | 212 |
UVM_INFO @ 888044703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 68295356934445822665933188377212140467942825208521834260112198397171711217886 | 154 |
UVM_INFO @ 334356039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 16643301775614002466113979644869066573786560243956776824188225948589013030771 | 176 |
UVM_INFO @ 1504272154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 8991740664324388138177437715418629535106676110039043503022261452695822239242 | 194 |
UVM_INFO @ 192018860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 7952181534013152204959902691689003282664380335732126120019560839243211303282 | 210 |
UVM_INFO @ 158490929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 8 test runs | |||
| alert_handler_stress_all_with_rand_reset | 67358605815249989517034269391160811318257047610694624348675177078475088796811 | 116 |
UVM_INFO @ 1555419003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 210660067362913670318468971610773613464960926425010084163761001987272146416 | 167 |
UVM_INFO @ 6900714444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 83081450225390179811344824109495276111444217870106021062625948451663861862123 | 82 |
UVM_INFO @ 406983861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 54795493540672255007320473103890193340967846668554077183269187224201219265886 | 134 |
UVM_INFO @ 11168444862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 75827967925977495137342590529357429284940959571616420357495104233361020095348 | 161 |
UVM_INFO @ 1872765358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 43967304964518887241754675141869529000278681289479003446522646054807512317647 | 125 |
UVM_INFO @ 827088190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 36135341981437682936178050009380844378706055997294537763490187081147704826917 | 92 |
UVM_INFO @ 786244822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 60589069802035539304189334845466165215870351542465047978137191549986465816788 | 116 |
UVM_INFO @ 1801617888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 2 test runs | |||
| alert_handler_ping_timeout | 100528527940384284512606292538055056461707249491318791985995614705765389051371 | 81 |
UVM_INFO @ 102422251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 60578686873300614859745935974842729795854074740578072303059407861047609385471 | 80 |
UVM_INFO @ 1831852196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1199) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. | 1 test run | |||
| alert_handler_stress_all_with_rand_reset | 58154685900337029312271011780411391647812341186331606183939361103615168058827 | 246 |
UVM_INFO @ 2755505472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:343) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) | 1 test run | |||
| alert_handler_stress_all | 77838791998811763062216061126997440356505061787150979448794212683897251315579 | 155 |
UVM_INFO @ 53504615509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 1 test run | |||
| alert_handler_lpg | 19117764837670931330451749960702057976361451279216300058623345287355371634996 | None | ||