Simulation Results: chip

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.44 %
  • code
  • 82.94 %
  • assert
  • 98.00 %
  • func
  • 99.38 %
  • line
  • 94.84 %
  • branch
  • 94.72 %
  • cond
  • 92.94 %
  • toggle
  • 75.05 %
  • FSM
  • 57.14 %
Validation stages
V1
96.88%
V2
88.14%
V2S
83.33%
V3
84.28%
unmapped
58.06%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 318.530s 3622.857us 3 3 100.00
chip_sw_example_rom 142.780s 3502.238us 3 3 100.00
chip_sw_example_manufacturer 283.910s 3515.782us 3 3 100.00
chip_sw_example_concurrency 311.960s 4369.720us 3 3 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 265.090s 5413.065us 1 1 100.00
csr_rw 5 5 100.00
chip_csr_rw 809.470s 6451.282us 5 5 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 568.720s 6420.707us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 6081.500s 28354.650us 1 1 100.00
csr_mem_rw_with_rand_reset 1 5 20.00
chip_csr_mem_rw_with_rand_reset 1115.110s 13816.931us 1 5 20.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
chip_csr_aliasing 6081.500s 28354.650us 1 1 100.00
chip_csr_rw 809.470s 6451.282us 5 5 100.00
xbar_smoke 50 50 100.00
xbar_smoke 11.150s 231.317us 50 50 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 495.780s 5250.176us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 495.780s 5250.176us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 495.780s 5250.176us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 602.270s 4687.719us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 602.270s 4687.719us 5 5 100.00
chip_sw_uart_tx_rx_idx1 557.960s 5184.364us 5 5 100.00
chip_sw_uart_tx_rx_idx2 614.710s 5397.571us 5 5 100.00
chip_sw_uart_tx_rx_idx3 625.590s 4923.813us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2571.710s 13699.556us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2485.700s 13886.484us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1542.910s 14015.801us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 400.680s 6387.928us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 400.680s 6387.928us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 312.590s 4035.034us 3 3 100.00
chip_sw_sleep_pin_wake 3 3 100.00
chip_sw_sleep_pin_wake 275.230s 3116.658us 3 3 100.00
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 354.430s 4698.385us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1175.440s 14772.377us 5 5 100.00
chip_tap_straps_testunlock0 474.970s 6713.585us 5 5 100.00
chip_tap_straps_rma 621.380s 7957.753us 5 5 100.00
chip_tap_straps_prod 1265.150s 14051.374us 5 5 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 808.460s 7853.895us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 808.460s 7853.895us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 1060.920s 10047.550us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 2602.510s 16161.928us 0 3 0.00
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 551.100s 5020.383us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 835.530s 6371.530us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5324.020s 19425.956us 3 3 100.00
chip_sw_aes_enc_jitter_en 248.970s 3513.978us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1188.270s 8671.507us 3 3 100.00
chip_sw_hmac_enc_jitter_en 281.470s 3812.680us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 2463.510s 13481.058us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 329.510s 4398.696us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 672.960s 6910.394us 3 3 100.00
chip_sw_clkmgr_jitter 306.000s 4037.889us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 307.120s 3691.044us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 8 8 100.00
chip_sw_sensor_ctrl_alert 1074.650s 12949.341us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 376.540s 5799.387us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 265.200s 3401.361us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 376.540s 5799.387us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 290.400s 2950.322us 3 3 100.00
chip_sw_aes_smoketest 312.730s 2941.249us 3 3 100.00
chip_sw_aon_timer_smoketest 364.010s 4214.677us 3 3 100.00
chip_sw_clkmgr_smoketest 291.540s 4400.839us 3 3 100.00
chip_sw_csrng_smoketest 254.980s 3563.210us 3 3 100.00
chip_sw_entropy_src_smoketest 1291.680s 7047.957us 3 3 100.00
chip_sw_gpio_smoketest 310.860s 3938.707us 3 3 100.00
chip_sw_hmac_smoketest 322.720s 3184.835us 3 3 100.00
chip_sw_kmac_smoketest 323.060s 3125.256us 3 3 100.00
chip_sw_otbn_smoketest 1755.120s 9280.624us 3 3 100.00
chip_sw_pwrmgr_smoketest 515.980s 6835.985us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 534.520s 6858.182us 3 3 100.00
chip_sw_rv_plic_smoketest 252.230s 3657.465us 3 3 100.00
chip_sw_rv_timer_smoketest 315.760s 3701.795us 3 3 100.00
chip_sw_rstmgr_smoketest 234.890s 2730.650us 3 3 100.00
chip_sw_sram_ctrl_smoketest 234.700s 4278.315us 3 3 100.00
chip_sw_uart_smoketest 329.100s 4168.349us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 285.020s 3485.465us 3 3 100.00
chip_sw_rom_functests 0 3 0.00
rom_keymgr_functest 556.410s 6231.417us 0 3 0.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 13885.020s 60566.197us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 4428.390s 19557.216us 3 3 100.00
chip_sw_rom_raw_unlock 2 3 66.67
rom_raw_unlock 1169.350s 16121.173us 2 3 66.67
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 1570.670s 15732.713us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 1337.940s 14377.228us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 12020.510s 55506.911us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 13073.170s 58235.699us 3 3 100.00
tl_d_oob_addr_access 1 30 3.33
chip_tl_errors 279.250s 3346.762us 1 30 3.33
tl_d_illegal_access 1 30 3.33
chip_tl_errors 279.250s 3346.762us 1 30 3.33
tl_d_outstanding_access 12 12 100.00
chip_csr_aliasing 6081.500s 28354.650us 1 1 100.00
chip_same_csr_outstanding 3524.080s 28893.010us 5 5 100.00
chip_csr_hw_reset 265.090s 5413.065us 1 1 100.00
chip_csr_rw 809.470s 6451.282us 5 5 100.00
tl_d_partial_access 12 12 100.00
chip_csr_aliasing 6081.500s 28354.650us 1 1 100.00
chip_same_csr_outstanding 3524.080s 28893.010us 5 5 100.00
chip_csr_hw_reset 265.090s 5413.065us 1 1 100.00
chip_csr_rw 809.470s 6451.282us 5 5 100.00
xbar_base_random_sequence 50 50 100.00
xbar_random 85.960s 2306.177us 50 50 100.00
xbar_random_delay 300 300 100.00
xbar_smoke_zero_delays 7.880s 53.938us 50 50 100.00
xbar_smoke_large_delays 92.790s 8918.775us 50 50 100.00
xbar_smoke_slow_rsp 93.260s 6588.432us 50 50 100.00
xbar_random_zero_delays 54.900s 552.830us 50 50 100.00
xbar_random_large_delays 474.320s 55067.492us 50 50 100.00
xbar_random_slow_rsp 432.230s 30542.519us 50 50 100.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 54.880s 1048.242us 50 50 100.00
xbar_error_and_unmapped_addr 67.330s 1431.048us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 87.660s 2214.090us 50 50 100.00
xbar_error_and_unmapped_addr 67.330s 1431.048us 50 50 100.00
xbar_all_access_same_device 100 100 100.00
xbar_access_same_device 147.610s 3199.475us 50 50 100.00
xbar_access_same_device_slow_rsp 1128.490s 88146.949us 50 50 100.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 71.230s 2287.301us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 508.690s 15154.448us 50 50 100.00
xbar_stress_all_with_error 584.760s 16029.054us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 722.920s 13385.417us 50 50 100.00
xbar_stress_all_with_reset_error 812.740s 17327.330us 50 50 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 4428.390s 19557.216us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 4115.350s 36558.427us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 4204.130s 15450.813us 3 3 100.00
rom_e2e_boot_policy_valid 14 15 93.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 3401.050s 11752.895us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 138.140s 2852.035us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 4523.050s 15275.003us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 4192.970s 15987.002us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3948.190s 15726.439us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 3291.780s 12203.138us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 4563.540s 15692.998us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 4444.680s 17874.683us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 4554.860s 17085.260us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 4007.710s 14926.980us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 5846.110s 18514.975us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 7776.120s 27338.079us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 7417.910s 24543.449us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 7142.830s 25324.414us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 7290.220s 23696.227us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 5924.660s 18642.212us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 7330.620s 24152.378us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 7491.040s 24998.912us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 7299.880s 23094.657us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 7382.620s 23172.152us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 3292.540s 13762.428us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 4244.620s 15350.638us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3998.460s 18154.750us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3897.380s 15096.979us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3893.420s 14324.747us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 3179.900s 11911.902us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3932.750s 14969.865us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3896.890s 15679.086us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 4037.450s 16061.043us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3916.130s 14211.128us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 3376.420s 13996.645us 3 3 100.00
rom_e2e_asm_init_dev 4716.450s 20143.827us 3 3 100.00
rom_e2e_asm_init_prod 4444.530s 17524.889us 3 3 100.00
rom_e2e_asm_init_prod_end 4438.960s 18696.100us 3 3 100.00
rom_e2e_asm_init_rma 4297.410s 16745.109us 3 3 100.00
rom_e2e_keymgr_init 5 9 55.56
rom_e2e_keymgr_init_rom_ext_meas 8305.180s 28505.939us 1 3 33.33
rom_e2e_keymgr_init_rom_ext_no_meas 8398.160s 30104.553us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_invalid_meas 8132.750s 30970.033us 2 3 66.67
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 4888.940s 23090.387us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.196s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.196s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 328.110s 4270.274us 3 3 100.00
chip_sw_aes_enc_jitter_en 248.970s 3513.978us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 277.260s 2979.952us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 326.970s 3822.254us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 2480.120s 14284.709us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 332.120s 3106.268us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 489.200s 6026.778us 3 3 100.00
chip_sw_all_escalation_resets 92 100 92.00
chip_sw_all_escalation_resets 777.750s 7820.488us 92 100 92.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 792.000s 5688.533us 3 3 100.00
chip_plic_all_irqs_10 464.360s 3943.057us 3 3 100.00
chip_plic_all_irqs_20 565.470s 5194.896us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 367.060s 4193.630us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1949.660s 18484.847us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 499.690s 6049.198us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 336.940s 4322.873us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.186s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2236.410s 12120.623us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1398.080s 7575.604us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1217.010s 8188.142us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 3 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14400.183s 0.000us 0 3 0.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 482.420s 4627.416us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 515.980s 6835.985us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 482.420s 4627.416us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 659.600s 8682.240us 0 3 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 659.600s 8682.240us 0 3 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 709.630s 9445.195us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 647.530s 6376.095us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 960.980s 6582.757us 3 3 100.00
chip_sw_aes_idle 326.970s 3822.254us 3 3 100.00
chip_sw_hmac_enc_idle 322.990s 3780.930us 3 3 100.00
chip_sw_kmac_idle 274.140s 3315.690us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 554.880s 5631.708us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 555.290s 5121.730us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 591.750s 7221.516us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 558.560s 7339.888us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1693.570s 15191.669us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 640.320s 4796.418us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 609.760s 5185.127us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 607.340s 4856.618us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 592.750s 5293.399us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 609.920s 5187.608us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 654.930s 5501.501us 3 3 100.00
chip_sw_ast_clk_outputs 1060.920s 10047.550us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1279.370s 15574.494us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 607.340s 4856.618us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 592.750s 5293.399us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 551.100s 5020.383us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 835.530s 6371.530us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5324.020s 19425.956us 3 3 100.00
chip_sw_aes_enc_jitter_en 248.970s 3513.978us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1188.270s 8671.507us 3 3 100.00
chip_sw_hmac_enc_jitter_en 281.470s 3812.680us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 2463.510s 13481.058us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 329.510s 4398.696us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 672.960s 6910.394us 3 3 100.00
chip_sw_clkmgr_jitter 306.000s 4037.889us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 258.170s 3313.080us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 589.980s 5568.265us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 893.520s 8211.473us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 5753.270s 25889.438us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 301.810s 3204.268us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 253.150s 3280.876us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 2067.060s 14313.749us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 319.040s 4087.909us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 633.220s 6077.398us 3 3 100.00
chip_sw_flash_init_reduced_freq 2447.710s 33238.522us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 24485.560s 139541.867us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 1060.920s 10047.550us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 555.640s 5716.123us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 391.330s 4180.790us 3 3 100.00
chip_sw_clkmgr_escalation_reset 92 100 92.00
chip_sw_all_escalation_resets 777.750s 7820.488us 92 100 92.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2236.410s 12120.623us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 2994.490s 24495.527us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 2 3 66.67
chip_sw_csrng_fuse_en_sw_app_read_test 511.600s 5522.385us 2 3 66.67
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 847.500s 10793.602us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 299.540s 3477.330us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 6591.780s 25124.804us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 304.540s 3809.803us 3 3 100.00
chip_sw_edn_entropy_reqs 1168.860s 7628.941us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 304.540s 3809.803us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 2994.490s 24495.527us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 269.560s 3030.990us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 2031.680s 23263.843us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 797.760s 6001.963us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 835.530s 6371.530us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 565.540s 5101.246us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 551.100s 5020.383us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 6270.270s 45896.511us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 2031.680s 23263.843us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 351.910s 4169.014us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 2249.610s 12607.632us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 306.120s 3823.881us 0 3 0.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 6270.270s 45896.511us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 306.120s 3823.881us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 306.120s 3823.881us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 306.120s 3823.881us 0 3 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 306.120s 3823.881us 0 3 0.00
chip_sw_flash_lc_escalate_en 92 100 92.00
chip_sw_all_escalation_resets 777.750s 7820.488us 92 100 92.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 765.750s 14868.987us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 846.260s 5754.126us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 723.970s 7071.766us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 723.970s 7071.766us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 316.670s 4119.764us 3 3 100.00
chip_sw_hmac_enc_jitter_en 281.470s 3812.680us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 322.990s 3780.930us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 2142.600s 10981.229us 3 3 100.00
chip_sw_hmac_multistream_mode 0 3 0.00
chip_sw_hmac_multistream 2609.570s 12018.618us 0 3 0.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 681.050s 6165.493us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 607.950s 5634.642us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 767.390s 5768.106us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 467.450s 4817.082us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 2249.610s 12607.632us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 2463.510s 13481.058us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 2740.650s 14803.747us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 2480.120s 14284.709us 3 3 100.00
chip_sw_keymgr_sideload_otbn 0 3 0.00
chip_sw_keymgr_sideload_otbn 6828.700s 20018.537us 0 3 0.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 285.430s 3678.737us 3 3 100.00
chip_sw_kmac_mode_kmac 314.060s 3836.645us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 329.510s 4398.696us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 2249.610s 12607.632us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 273.030s 3877.981us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 2411.010s 11400.006us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 274.140s 3315.690us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 489.200s 6026.778us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1175.440s 14772.377us 5 5 100.00
chip_tap_straps_rma 621.380s 7957.753us 5 5 100.00
chip_tap_straps_prod 1265.150s 14051.374us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 224.230s 3502.839us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 1707.310s 10613.956us 3 3 100.00
chip_sw_lc_ctrl_broadcast 76 84 90.48
chip_sw_flash_ctrl_lc_rw_en 306.120s 3823.881us 0 3 0.00
chip_sw_flash_rma_unlocked 6270.270s 45896.511us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 313.050s 4018.654us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 984.980s 10700.004us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 964.680s 9216.987us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 963.530s 8519.820us 0 3 0.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_sw_keymgr_key_derivation 2249.610s 12607.632us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 603.500s 9940.146us 3 3 100.00
chip_sw_sram_ctrl_execution_main 966.740s 12239.753us 3 3 100.00
chip_prim_tl_access 765.750s 14868.987us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1279.370s 15574.494us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 640.320s 4796.418us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 609.760s 5185.127us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 607.340s 4856.618us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 592.750s 5293.399us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 609.920s 5187.608us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 654.930s 5501.501us 3 3 100.00
chip_tap_straps_dev 1175.440s 14772.377us 5 5 100.00
chip_tap_straps_rma 621.380s 7957.753us 5 5 100.00
chip_tap_straps_prod 1265.150s 14051.374us 5 5 100.00
chip_rv_dm_lc_disabled 682.040s 13108.487us 1 3 33.33
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 253.490s 3403.004us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 154.830s 3358.092us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 131.560s 3269.415us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 282.260s 4612.045us 3 3 100.00
chip_lc_test_locked 4 6 66.67
chip_sw_lc_walkthrough_testunlocks 3287.730s 47089.318us 3 3 100.00
chip_rv_dm_lc_disabled 682.040s 13108.487us 1 3 33.33
chip_sw_lc_walkthrough 6 15 40.00
chip_sw_lc_walkthrough_dev 1190.180s 11910.220us 0 3 0.00
chip_sw_lc_walkthrough_prod 1270.970s 26923.867us 0 3 0.00
chip_sw_lc_walkthrough_prodend 1191.890s 11603.588us 3 3 100.00
chip_sw_lc_walkthrough_rma 668.240s 9227.864us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 3287.730s 47089.318us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 8 9 88.89
chip_sw_lc_ctrl_volatile_raw_unlock 186.800s 3499.716us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 170.700s 3083.347us 2 3 66.67
rom_volatile_raw_unlock 163.260s 3639.203us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 5182.230s 17768.788us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5324.020s 19425.956us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 960.980s 6582.757us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 960.980s 6582.757us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 960.980s 6582.757us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 431.390s 3376.918us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_sw_otp_ctrl_keys 15 15 100.00
chip_sw_flash_init 2031.680s 23263.843us 3 3 100.00
chip_sw_otbn_mem_scramble 431.390s 3376.918us 3 3 100.00
chip_sw_keymgr_key_derivation 2249.610s 12607.632us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 631.810s 6697.878us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 314.410s 4236.696us 3 3 100.00
chip_sw_otp_ctrl_entropy 15 15 100.00
chip_sw_flash_init 2031.680s 23263.843us 3 3 100.00
chip_sw_otbn_mem_scramble 431.390s 3376.918us 3 3 100.00
chip_sw_keymgr_key_derivation 2249.610s 12607.632us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 631.810s 6697.878us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 314.410s 4236.696us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 592.230s 6651.828us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 224.230s 3502.839us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 313.050s 4018.654us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 984.980s 10700.004us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 964.680s 9216.987us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 963.530s 8519.820us 0 3 0.00
chip_sw_lc_ctrl_transition 1272.470s 15419.984us 15 15 100.00
chip_prim_tl_access 765.750s 14868.987us 3 3 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 765.750s 14868.987us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1330.080s 8788.116us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 3 0.00
chip_sw_pwrmgr_full_aon_reset 294.780s 6648.000us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1822.380s 31647.093us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 445.330s 8529.809us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 560.930s 7875.450us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 689.070s 7798.000us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1653.300s 26488.686us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 6 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 699.710s 11195.244us 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 659.600s 8682.240us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1325.220s 13992.938us 3 3 100.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 624.520s 7049.013us 3 3 100.00
chip_sw_pwrmgr_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_full_aon_reset 294.780s 6648.000us 0 3 0.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 522.390s 6930.246us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 990.180s 13158.937us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 646.480s 10215.954us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 292.660s 4100.550us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 861.540s 13203.400us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1156.550s 9472.271us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1455.580s 15169.399us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2859.500s 32796.112us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 300.430s 3901.827us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 92 100 92.00
chip_sw_all_escalation_resets 777.750s 7820.488us 92 100 92.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 603.500s 9940.146us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 603.500s 9940.146us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 1455.580s 15169.399us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 861.540s 13203.400us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 624.520s 7049.013us 3 3 100.00
chip_sw_pwrmgr_smoketest 515.980s 6835.985us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 534.470s 5643.081us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 885.450s 9412.594us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 543.600s 5586.260us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1949.660s 18484.847us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 280.180s 3959.354us 3 3 100.00
chip_sw_rstmgr_escalation_reset 92 100 92.00
chip_sw_all_escalation_resets 777.750s 7820.488us 92 100 92.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1398.080s 7575.604us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 694.880s 4663.733us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 813.330s 5823.041us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 371.310s 4292.441us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 314.410s 4236.696us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 885.450s 9412.594us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 885.450s 9412.594us 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 292.380s 3534.853us 3 3 100.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1989.620s 17278.999us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1806.750s 16917.084us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 534.470s 5643.081us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 336.900s 4183.195us 0 3 0.00
chip_rv_dm_access_after_wakeup 0 3 0.00
chip_sw_rv_dm_access_after_wakeup 2127.120s 13681.984us 0 3 0.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 621.380s 7957.753us 5 5 100.00
chip_rv_dm_lc_disabled 1 3 33.33
chip_rv_dm_lc_disabled 682.040s 13108.487us 1 3 33.33
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 792.000s 5688.533us 3 3 100.00
chip_plic_all_irqs_10 464.360s 3943.057us 3 3 100.00
chip_plic_all_irqs_20 565.470s 5194.896us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 265.330s 4148.289us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 282.830s 3265.789us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 4428.390s 19557.216us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 518.760s 5281.879us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 334.020s 4250.932us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 326.500s 3623.921us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 251.300s 3634.051us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 631.810s 6697.878us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 672.960s 6910.394us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 961.810s 11768.281us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 938.160s 10166.480us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 966.740s 12239.753us 3 3 100.00
chip_sw_sram_lc_escalation 98 106 92.45
chip_sw_all_escalation_resets 777.750s 7820.488us 92 100 92.00
chip_sw_data_integrity_escalation 808.460s 7853.895us 6 6 100.00
chip_sw_sysrst_ctrl_reset 5 6 83.33
chip_sw_pwrmgr_sysrst_ctrl_reset 1156.550s 9472.271us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1685.550s 23339.182us 2 3 66.67
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 314.760s 3840.501us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 425.690s 5074.763us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 482.750s 5715.359us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 2 3 66.67
chip_sw_sysrst_ctrl_reset 1685.550s 23339.182us 2 3 66.67
chip_sw_sysrst_ctrl_sleep_reset 2 3 66.67
chip_sw_sysrst_ctrl_reset 1685.550s 23339.182us 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3375.910s 20980.634us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3375.910s 20980.634us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 608.290s 6708.079us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.196s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 210.030s 3148.994us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 300.480s 3675.959us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 453.400s 5182.310us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 514.660s 4990.527us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1696.610s 8923.632us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 7752.480s 31988.685us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2680.500s 12945.917us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 249.580s 3553.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 286.360s 3298.357us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 2 3 66.67
chip_sw_rv_core_ibex_lockstep_glitch 273.950s 3211.629us 2 3 66.67
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 17316.250s 69626.272us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1693.680s 7318.435us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 617.170s 7826.915us 0 1 0.00
rom_e2e_jtag_debug_dev 352.680s 3970.284us 0 1 0.00
rom_e2e_jtag_debug_rma 367.760s 5423.916us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 156.370s 4078.874us 0 1 0.00
rom_e2e_jtag_inject_dev 104.240s 2024.876us 0 1 0.00
rom_e2e_jtag_inject_rma 114.100s 2394.911us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 75.163s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 405.380s 4645.636us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 525.850s 3135.661us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1040.330s 5991.440us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1836.030s 10023.919us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 392.840s 3348.025us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 890.130s 6312.649us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 238.730s 2955.108us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 301.730s 3237.547us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 2 3 66.67
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 574.650s 7769.029us 2 3 66.67
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 603.860s 5644.997us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1455.580s 15169.399us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 617.170s 7826.915us 0 1 0.00
rom_e2e_jtag_debug_dev 352.680s 3970.284us 0 1 0.00
rom_e2e_jtag_debug_rma 367.760s 5423.916us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 700.690s 7660.390us 3 3 100.00
chip_sw_plic_alerts 92 100 92.00
chip_sw_all_escalation_resets 777.750s 7820.488us 92 100 92.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.191s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.191s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 336.520s 3828.536us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 602.270s 4687.719us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 4330.960s 19752.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 18 31 58.06
chip_sival_flash_info_access 341.670s 3976.187us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 34.550s 10.220us 0 3 0.00
chip_sw_otp_ctrl_rot_auth_config 10.160s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 301.470s 3628.314us 3 3 100.00
chip_sw_otp_ctrl_descrambling 319.970s 3396.251us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 373.470s 4158.033us 3 3 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 13.726s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 366.030s 3332.321us 3 3 100.00
ate_bootstrap_flash_erase 964.310s 10010.280us 0 3 0.00
ate_bootstrap_one_frame 10413.070s 44586.059us 3 3 100.00
ate_bootstrap_disjoint 10800.198s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 44327157257150024933576152894581981209099434799788177352031098614269085979301 311
UVM_INFO @ 4140.803036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97642250122768785637378843563855407895996088173999283682238166330807307344489 311
UVM_INFO @ 2787.114552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71444564205567648846105499821179940058074018163246712178368798024473319203373 311
UVM_INFO @ 3636.897316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 1250528259856512954841288045000352160755859276552080260801654575066456382241 311
UVM_INFO @ 3198.532034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 10463885349080794153640997959361307980457963538225113802122223385506006849115 311
UVM_INFO @ 3564.880280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57402473129075562555619358642499969717033745824076181423463681547767246332816 311
UVM_INFO @ 3296.567790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44765944642174310580873497382967797924858929256348794269160496546300878792744 311
UVM_INFO @ 4250.640992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24586804799840475680543411066827012047075510582054772914964483898377615729904 311
UVM_INFO @ 2947.590935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 66589412646619714657109479315866371079759299791819518997293577779682355027034 311
UVM_INFO @ 4028.578667 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21394713996745904693978099309242030339908368278095506571973632114834630962181 311
UVM_INFO @ 3596.701348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100008176697762165742307448399750907086168276040271759868027015400505838069844 311
UVM_INFO @ 3802.075480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91273776367138649731417481147853475619922259590491865414624194732333266163752 311
UVM_INFO @ 3053.653400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 11559858661975901808521422775114113949604014417146155044421205866512824802151 311
UVM_INFO @ 2679.369046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85657808834425358392061562529046144564086406046503657499806029248575052764998 311
UVM_INFO @ 2747.490880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44566031534543581056820550727284303916253284579850647488285517196227164857231 311
UVM_INFO @ 3425.309523 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34875858421233299993475770454561813630168283678082982406028208207559716131577 311
UVM_INFO @ 3349.179033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28918192528699468033441358919752882124696308146797580226722298309625557529849 311
UVM_INFO @ 4037.591288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40600735154431114291534080872098780962967690778199548516859167135257889120281 311
UVM_INFO @ 2760.446568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100327524274870513083216022535834939511370110923125245367035317189869198483039 311
UVM_INFO @ 2963.098190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102591939393334506885777570070245382948685571637533524969446333171760075036777 311
UVM_INFO @ 2917.632465 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 66279457044207677740431383780479196313362458014584843169841117481077477849703 311
UVM_INFO @ 4122.678417 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28385059001441922404386894491110611319773615886359830104237481049097264042381 311
UVM_INFO @ 2993.262096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53744294239600422790913938707847602333255493622354549464712491700676911976972 311
UVM_INFO @ 2759.839399 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92561059870391748283305032406003229827493775713830438908254336829898413478149 311
UVM_INFO @ 3077.386632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14278981086551564774493379018016282224349514119587171566602158116766533752947 311
UVM_INFO @ 3250.461124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40636578121611327891901997895187402814013657382472290125876595826041323459975 311
UVM_INFO @ 4122.627384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99708347786225663934738995350422639574152477336528590204957785928036301930278 311
UVM_INFO @ 3410.677935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16962780354682610734879162044449885996141164541545825278183049038793644359059 311
UVM_INFO @ 2821.037040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48422233451160127966797335878015955855332286893965371469375378896199690828301 311
UVM_INFO @ 3606.037408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33006585114536351054612913038997439866274382049147409637483591378660188841385 311
UVM_INFO @ 3239.105000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101884282086848747528809338467653089633577847958123845193099810421081701122114 311
UVM_INFO @ 3532.912541 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102982819923364943305324524107686316721184474745621428214570335975403974948227 311
UVM_INFO @ 3111.268704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44547953374630820848730929780750650016374495951517881934916088718939303733209 311
UVM_INFO @ 4128.781643 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45702082548571141059746738170292523841864349039777551391074419218278408305428 311
UVM_INFO @ 4322.873294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 75400320328758161802880744457155502605617305666793287900658648448818411466633 311
UVM_INFO @ 3899.330196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95975845636970710041668791310706612077757782711515510195243334114078483377814 311
UVM_INFO @ 3736.667556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96437774459558898077967734640788756414830044836406816511828708020380188498666 311
UVM_INFO @ 3622.062034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26820601816452040501250382854228718520375792978266386343112283005523578940600 311
UVM_INFO @ 3266.343320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68285139231929465260230698023389043054927952337006829319305943463693847541609 311
UVM_INFO @ 3266.633000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85919824321155793948099006459525183261656325219274544183984532034082762002037 311
UVM_INFO @ 3365.213238 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49078059733717451431529133068321587650942312781431810137631883455483165965273 311
UVM_INFO @ 4041.949191 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 13392957260947907898431670061452570816532065781259356443246108736291187919518 311
UVM_INFO @ 3325.686039 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97241827174429668658593054071284897225484777303715822668713552678763842812404 311
UVM_INFO @ 3844.674172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 10434465375850405997534128617091511111349172898693321364533092717156331490190 311
UVM_INFO @ 3769.746137 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86446117927234939565895373819349382320582742200469559134497076083195743291686 311
UVM_INFO @ 3088.516368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104416451829405726679223418812958785456268458548700343200497946957235961526844 311
UVM_INFO @ 4194.178550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 66969074295316486952888261710686407867041302783671602462570115628590561838059 311
UVM_INFO @ 3287.625965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74403750073363488476526919844423401507848750907749487328103817972950244154609 311
UVM_INFO @ 3878.687669 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59067285200115895140934337934982483348916076354747780713486013851668190399201 311
UVM_INFO @ 2994.927568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23240436859078855791972646684156582635961773197642691693464067628025647213042 311
UVM_INFO @ 4274.284102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31897443390217737450682107016167242846468245083841142343936083917689914621556 311
UVM_INFO @ 3656.146824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79232229300733968139826898471793514271211824946686940162631604047137742167671 311
UVM_INFO @ 3005.054940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21334395703664549416743245903481971881622617951122024553493847618841794950036 311
UVM_INFO @ 4145.022528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81315139491486803504165746224576107091665486929024722714041004014895458003222 311
UVM_INFO @ 3384.041110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90208683568582870747347657500630798317420602311723657319349882975352691181897 311
UVM_INFO @ 2773.416232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41592208806862841641683458028695134981177363035283657656923824020842105338873 311
UVM_INFO @ 3199.338664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62072294978983933439278932698712132782811696401768070122524293565362985613082 311
UVM_INFO @ 3667.515208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3619934738829972884342583376104416595334963330587720806966549038261990538279 311
UVM_INFO @ 3313.062328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19067350356461981449527094612726997788554443179485976529504769458857475195994 311
UVM_INFO @ 3705.257250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31024486426028632170521858196223821309530250600004230340583334649037985249416 311
UVM_INFO @ 3429.308553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108413071553497235847764041051177954821899977412924020448599038743813267769632 311
UVM_INFO @ 3851.229618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45905437226525984885436035473383770225883526658353402353602216825502831328103 311
UVM_INFO @ 2574.979795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79047208815526379395929161746476101181252639297138436052790390648179506419455 311
UVM_INFO @ 4136.958090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 72471279862234538065624508177110343058948125413006665273572777850445410013963 311
UVM_INFO @ 3221.627620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36534908827739495072984061113723196731310465639312102482318541407403825243613 311
UVM_INFO @ 3418.073286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9123779443574288269730500818698024364833370363102038994843338133553323301804 311
UVM_INFO @ 3153.932695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109474736104087905838545984710507634344678657891029300628577826754138387965447 311
UVM_INFO @ 3181.806856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 398278672485285824331506771774384742111180497139784182366417683226093934463 311
UVM_INFO @ 3286.792658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 5379698695141810676529000420638405258591454958640061377068025980128331898927 311
UVM_INFO @ 3081.243509 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71799045691335198211765262161269498245192945972937220597447449982495350967059 311
UVM_INFO @ 3837.567456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81836799790988522737118405648112053140428589892918906120276120309034759235237 311
UVM_INFO @ 3877.341293 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 13105444223020277208746264633830164542513770940107350396160808659915915020255 311
UVM_INFO @ 2972.156320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52166647884848886049770863195563650267475364163830686609636384020557032973421 311
UVM_INFO @ 3711.011088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45989285024983042366471921952550377459277809343655195866735943915590193715418 311
UVM_INFO @ 3548.795010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29587134939377166353999711257167076150874104934169120011624418956092248812376 311
UVM_INFO @ 3809.489922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28252716571325901259468589319799278254393365032374405275748463907830439134004 311
UVM_INFO @ 2957.290140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96779037102133976161841337443094552507807746778471398306070514195010920313771 311
UVM_INFO @ 2930.253562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 10145868434328424923915788515667583221686772489371139084416696744347207139182 311
UVM_INFO @ 4557.515000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19853035267197578133260699670739141454726699741411758808953215001689077974788 311
UVM_INFO @ 3282.196931 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93840391036266262367245233797726505140896340094351536720464921992015156655859 311
UVM_INFO @ 3656.790036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 18700652754046206073698536358446853043000297665969647112748571741949642466117 311
UVM_INFO @ 3033.596040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4992330571021982387163357861829929608436411940051033227958012749533231874537 311
UVM_INFO @ 3504.045935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62132412711601235813538428579457602861151770665594708865263900731993911241226 311
UVM_INFO @ 3156.184952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 76987845299175462985904265880167185204521498580436313588711695815112742028681 311
UVM_INFO @ 4344.401020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81153091615576280188064613778524046701366259418380528207858742041705716273993 311
UVM_INFO @ 4015.069684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23525844551902517155708546352522832708458584813747308381259035710942204388941 311
UVM_INFO @ 2695.408664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56632379205379275481510125683347854376615733961901688538256290315470735700088 311
UVM_INFO @ 2574.198196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6554444113172464335508554386145868926577332571482194023911280511932441521312 311
UVM_INFO @ 2997.894593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 37102945472050750519273400585458371543412844186692854959818562368917279713647 311
UVM_INFO @ 4325.912470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 80161838636143898485466570362148969466767810184325723861115480797572478795512 311
UVM_INFO @ 3084.657425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:615) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 33 test runs
chip_tl_errors 90276210708292115914606857214331381588162470232065661674961561077520485155365 220
TL item was: req: (cip_tl_seq_item@35401) { a_addr: 'h10698 a_data: 'ha4b97e97 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h19e3c d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2758.558337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 21796859210188850230437831525167853151583573756617616455032248173609895766359 220
TL item was: req: (cip_tl_seq_item@33475) { a_addr: 'h104e4 a_data: 'he75b6b4c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1998a d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2677.567328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 107465008715484060531966747190763110442593595366541192774481709533644908331960 227
TL item was: req: (cip_tl_seq_item@31825) { a_addr: 'h10638 a_data: 'h3936cb7e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1b65a d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3023.313797 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 114156802237399251425750983488817837488907734166600107689750369256056339010108 220
TL item was: req: (cip_tl_seq_item@35419) { a_addr: 'h10464 a_data: 'hfe2b6c9a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h1a94b d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3351.585201 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 93128613989812140376740947626940249304146320903086128795872764678616118578862 245
TL item was: req: (cip_tl_seq_item@220152) { a_addr: 'h106c0 a_data: 'hcd765baf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h27 a_opcode: 'h4 a_user: 'h1869d d_param: 'h0 d_source: 'h27 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 6833.116520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 35286508072266402819768828421862529196954409228853001007835904850105471227263 220
TL item was: req: (cip_tl_seq_item@35763) { a_addr: 'h10434 a_data: 'he71d08fb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1a51f d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3024.222544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 40260423983980846156229624545608133603520541120698533006864671818591409432503 227
TL item was: req: (cip_tl_seq_item@31951) { a_addr: 'h105ec a_data: 'hbcc14a41 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h18a6a d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2356.163309 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 86619216199489090082749689180559795153307214533787532068084489864332955200568 220
TL item was: req: (cip_tl_seq_item@36315) { a_addr: 'h1045c a_data: 'heca64126 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h18199 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2794.705133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 26751147429547976195284749380524652137920544718264332171586574190608354420315 227
TL item was: req: (cip_tl_seq_item@32037) { a_addr: 'h10520 a_data: 'haee34268 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h18a03 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3405.959038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 37457815220491265588841047301041165371589100220234681687647621928578115794584 220
TL item was: req: (cip_tl_seq_item@36525) { a_addr: 'h107e8 a_data: 'he74f281a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h18df9 d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2522.398000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 53195174963238883764784987816316269138871837060961970979220694340552190842487 220
TL item was: req: (cip_tl_seq_item@34807) { a_addr: 'h10580 a_data: 'h6cd576b8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h1a267 d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3333.497764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 65460594122167296543480193182290964213405897290866460749305725977067655376332 220
TL item was: req: (cip_tl_seq_item@31917) { a_addr: 'h10448 a_data: 'h7bbfec9c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h1a9f5 d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2373.634424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 100242723100893537168220743312952488684772475286985526159232690408707254669099 220
TL item was: req: (cip_tl_seq_item@35573) { a_addr: 'h104d0 a_data: 'h52a63e0a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1a90b d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2122.272692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 100642203610817080842672321034167530875183648771328939045789173511948217867383 221
TL item was: req: (cip_tl_seq_item@141539) { a_addr: 'h10520 a_data: 'hf016dc91 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h18a50 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3063.573972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 79733972770590824345462693626952542658395083964120938639313687106285826280152 220
TL item was: req: (cip_tl_seq_item@32213) { a_addr: 'h104b8 a_data: 'hccf7b6a7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h18df4 d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2738.768356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 59806966000491069618876451555395474661706961951103590043572299484662476483681 221
TL item was: req: (cip_tl_seq_item@196043) { a_addr: 'h10528 a_data: 'hb45e4e3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h19e97 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3346.761990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 34125419042816619457339139626987561002225932572651737636872007468512072399421 220
TL item was: req: (cip_tl_seq_item@31927) { a_addr: 'h1069c a_data: 'h2d5a6a46 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h27 a_opcode: 'h4 a_user: 'h19286 d_param: 'h0 d_source: 'h27 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3144.516982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 56724824331130207161117745391077636860170143462123662910173446000876033067258 220
TL item was: req: (cip_tl_seq_item@34433) { a_addr: 'h104e0 a_data: 'hab3b6381 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h19504 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2748.857799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 109008468706813445588015364919002594827780247566469179220884935066670595314018 220
TL item was: req: (cip_tl_seq_item@32419) { a_addr: 'h107d8 a_data: 'h194078c0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h1b1bd d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2893.926212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 15290711780610973058648516021560115520405877582467208907090496267454214029347 220
TL item was: req: (cip_tl_seq_item@35159) { a_addr: 'h10690 a_data: 'hffd7966 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h18a8b d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2534.999681 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 112391635342858034990116955369734956460030864189023047173445793857355205650057 220
TL item was: req: (cip_tl_seq_item@36199) { a_addr: 'h10100 a_data: 'ha73ee54 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h18187 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2402.346120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 112081529984653147610911442159318294790778262122500203231260616497051634632491 220
TL item was: req: (cip_tl_seq_item@35473) { a_addr: 'h1075c a_data: 'h7ba0d8cf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h18df3 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3847.749064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 7402223906124961814967529250420266131659274605841311932007801482216200451428 220
TL item was: req: (cip_tl_seq_item@36559) { a_addr: 'h104ac a_data: 'h6906f551 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h1a5df d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3467.176146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 28082114405115278249346575640701438370753104250421893646201550908899085792987 220
TL item was: req: (cip_tl_seq_item@33333) { a_addr: 'h107c8 a_data: 'h4b4aee46 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h19501 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2824.868850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 76245784904635771988391987767114560224898456979982515614941003525850761914345 220
TL item was: req: (cip_tl_seq_item@33931) { a_addr: 'h10460 a_data: 'h5fc70d43 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1a59e d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2753.380626 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 29859628884775685503675545559952788785158157840486652692867159541823576409609 220
TL item was: req: (cip_tl_seq_item@32423) { a_addr: 'h10600 a_data: 'hc5a1a3ef a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h19ee1 d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2609.621790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 36943978045133348721322640740975731406240940900817328142637706223389447442385 220
TL item was: req: (cip_tl_seq_item@32489) { a_addr: 'h10578 a_data: 'h218fa4e2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h192d1 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3180.846450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 59388373779822075861942118109205826951180713871246329959410414394535367780681 220
TL item was: req: (cip_tl_seq_item@36581) { a_addr: 'h107fc a_data: 'h232fc0d2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h1a5e1 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3225.062180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 17507812880637269317869080732128063606037028860910471961557803323115977538193 220
TL item was: req: (cip_tl_seq_item@31713) { a_addr: 'h10338 a_data: 'hb940b710 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1a26c d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2254.050988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 64272033889092645710951118775678007890547115912071425221575752613533451155978 220
TL item was: req: (cip_tl_seq_item@35655) { a_addr: 'h104e0 a_data: 'h2bd7ca1b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h19551 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3535.299168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 17520621601509917674097889515243402823560374947124607196436131390466069205527 220
TL item was: req: (cip_tl_seq_item@33775) { a_addr: 'h10424 a_data: 'h4df703a1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h181d4 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2831.784979 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 28873951834080564815891395231257421173920641465932907249433395180217928372023 220
TL item was: req: (cip_tl_seq_item@34539) { a_addr: 'h10654 a_data: 'h4e4012fc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h19e4b d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3487.567720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 69025619284955564637436145968114970812651902081175130154726018092701540099084 220
TL item was: req: (cip_tl_seq_item@35729) { a_addr: 'h10340 a_data: 'hff189365 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1a27f d_param: 'h0 d_source: 'h9 d_data: 'hc55513 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd33 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2973.907900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 15 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 84655517928940317298214213002238512391485174730198036223266485526681152181684 318
UVM_ERROR @ 5472.021500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5472.021500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 13918867997655285287398478880753279626561368112602162393956320781075742538768 330
UVM_ERROR @ 9626.061000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9626.061000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 30282445824169958293492835043525890390656547318071653343010269459660762542281 328
UVM_ERROR @ 8796.983000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8796.983000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 45295534291554657297212948058883169886282567350312374884801903014328364346009 319
UVM_ERROR @ 6278.012500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6278.012500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 100508182268688423754937187163500801425207589633352601449262459086428112970686 322
UVM_ERROR @ 7534.399500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7534.399500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 30335594487945132047787118371011469749223787950198478503535827599243794730848 347
UVM_ERROR @ 14769.666500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 14769.666500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 25056686502246580470861771172861546385191084978596138550541430119074330916601 330
UVM_ERROR @ 11195.244000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11195.244000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 60828674356285611861133464405923627625059663700606103308065930458545453834369 328
UVM_ERROR @ 8919.507000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8919.507000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 23386613569034042279684421742147050498564568165882576281905440355990643879682 322
UVM_ERROR @ 8682.240000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8682.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 11519660960418779780826364586200645324338168978461873664560261623490349501953 347
UVM_ERROR @ 13203.400000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13203.400000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 110930176561664405249363427037268353565072692088271924684489347041628110673855 317
UVM_ERROR @ 7455.492000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7455.492000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 55274026328918360573459976436404312830125256550531414690660729378036806322169 328
UVM_ERROR @ 7875.450000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7875.450000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 53270990234432112604058603010873430445719555033022047702594287499592798413650 319
UVM_ERROR @ 5800.346000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5800.346000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 27181357139411478936798932286618331141309376361892562672096171814731255968165 337
UVM_ERROR @ 25009.588000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 25009.588000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 112178751182455839403134738094492785439698115354832856054542949319438654398310 322
UVM_ERROR @ 10013.780000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10013.780000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 15 test runs
chip_sw_rv_timer_systick_test 66145814001949241992277452991810319903770307018783006850729852055158173230382 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 100637753977352881439222684474427083963176253419113197725422714499610402569293 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 4861567319785863135891241005058477373700995193563662454780709358308560665707 None
chip_sw_alert_handler_lpg_sleep_mode_pings 113833045404480193229392138950149034453972720856959597067291807060066326281585 None
ate_bootstrap_disjoint 8867123132352800029061232367781680278203561201582317856055963082530571448798 None
chip_sw_rv_timer_systick_test 7632552967287368761026655084079169056083524905500380326064899504156053973177 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 75648860508588528505524176300217149543788753252790865720108066548755763097862 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 26348480755384395561713829262882022368026845326174534367366408860049091657584 None
chip_sw_alert_handler_lpg_sleep_mode_pings 108729219142319175842948524603748270530080442520605399485949318759893900722164 None
ate_bootstrap_disjoint 102720053887865190989927427505809908346731945009487129274946855987573913234429 None
chip_sw_rv_timer_systick_test 17860979044837625534466486429857284780308671875502988418686350501926209468126 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 37189850312508657664755982737466562147386431121662437534032054520619450915962 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 93106876323629554734390577881092311001221139186252518733566118749705189899707 None
chip_sw_alert_handler_lpg_sleep_mode_pings 27438678478325515862079704814751577076365856580288753441589981898221576860356 None
ate_bootstrap_disjoint 81794829069493076929335318137045838011275072956811327929687176919744398334535 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 8 test runs
chip_sw_lc_walkthrough_dev 19448047315550208409883761179650199531582491718671386349324903356627750172871 372
UVM_INFO @ 11675.718447 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 25390524184834862823375082739905977918974660972028776144111131840907280341100 372
UVM_INFO @ 14847.558804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 17290675579358205369282167163233962839247648948036754692437793025746553446203 344
UVM_INFO @ 9227.863879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 88875917589244661277939556356992500833148192976900246254882616605189544462682 372
UVM_INFO @ 11910.220408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 45897538164164955467934070532364957331517479382021020688007710852400016593497 372
UVM_INFO @ 11053.672169 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 15999798351856085367956758000060230431299588425615838779681167084037761536577 344
UVM_INFO @ 7719.455544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 18898628548946370781014990716186218015686278854196066791195952367625359951625 372
UVM_INFO @ 10429.367560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 34638114587125715324239916158948530605421345666403652994785697589234871175945 344
UVM_INFO @ 5979.165820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 8 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 35173215061194520540325404694261900041039550571697474553367855273793479839207 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 90653389062750359958256398059739223144623850916162091279842405320479963729347 355
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 55770012881269825211002547297293392562340529170571221684823599388266639772989 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 39727760476405631835151365358557444134911187641562327940892570292921148597618 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 75407417477395770963221804416978794316056710973659497440170413782357534437683 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 36928052658809203564518386517119211263308397454311774804721514145568979624977 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 5291446817837812041676962457363086209496777449273285701260564700314549212243 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 26469119110966606180014424053425664605904176881057305984397147758082973854440 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 6 test runs
chip_sw_hmac_multistream 28318316448328950819114172460351823872730376298242972248519932861477423951484 380
UVM_INFO @ 12018.617595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 55963996741561362923988886534032657261491658595607446691515519125408510640827 339
UVM_INFO @ 20026.508100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 114894620792040082874586672796072260948259042971553546192739471849249017550211 354
UVM_INFO @ 12026.653180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 25975904830883538482210004585537160747213387694426918967239932642489443555689 339
UVM_INFO @ 20018.537300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 70699167284905601048997031408012375334177283970571849293935359267706204899087 380
UVM_INFO @ 12026.581712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 50834003138446415148175650816100036744807381089191041018626877798113282774540 339
UVM_INFO @ 20018.637678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 6 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 66158696615133541434758392147847382165392027520045334462884738633237603734338 None
---- STDERR ----
Another command (pid=3556537) is running. Waiting for it to complete on the server (server_pid=255911)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 110759723326550141962061453316820752750324096845853426028115474252543846488135 None
Another command (pid=255825) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=256384) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=256305) is running. Waiting for it to complete on the server (server_pid=255911)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 23143937393590576168201470035536529042657901396913588466986306419719494397354 None
Another command (pid=285051) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=287542) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=285477) is running. Waiting for it to complete on the server (server_pid=255911)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 97664550563084964963386297375600602237633071132397427786948609292009557353372 None
Another command (pid=271690) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=290880) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=291335) is running. Waiting for it to complete on the server (server_pid=255911)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 65644609821053025547758450473365369364461492700755994618931615570131807287566 None
---- STDERR ----
Another command (pid=1277650) is running. Waiting for it to complete on the server (server_pid=255911)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 23078544450389143941732188274801220508751208212292949650138444479887218962508 None
Another command (pid=359210) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=358086) is running. Waiting for it to complete on the server (server_pid=255911)...
Another command (pid=342596) is running. Waiting for it to complete on the server (server_pid=255911)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1095)] Unexpected fault 6 test runs
chip_sw_all_escalation_resets 58455230818780960694677311564333627316523496626507495794747263069950028223394 313
UVM_INFO @ 4305.888854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 69989867875683606825775812556593520825683475853785761477570546766864450638668 313
UVM_INFO @ 3221.532717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 89244659783851160777892304942631411540099398376435232888612259620527296180369 313
UVM_INFO @ 3735.172947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 27450087762351798405942949327897043762522022070387576267504302249262133306365 313
UVM_INFO @ 3028.787360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 110818391231985781801766643438785328826009571298189000607092182605576245860749 313
UVM_INFO @ 3384.293952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 53880893436585127601757662042437581561872721597316749570825817055210930173420 313
UVM_INFO @ 3600.417360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 4 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 62162627965825820388978440056027061305042337419617049838664211072686058665700 316
UVM_ERROR @ 4100.549560 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4100.549560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 3840242367691323870923733370314401992212435268692769928225730553489862638951 316
UVM_ERROR @ 3324.042350 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3324.042350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 113977558850642585096936090307107111528513025150661322362035770386490580490222 357
UVM_ERROR @ 13158.937125 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 13158.937125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 76917016060368471554629234463230197467264696099974201528372589267689485396751 316
UVM_ERROR @ 3403.877336 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3403.877336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 3 test runs
chip_sw_rstmgr_rst_cnsty_escalation 105450256793279447569262615449250384095953824468035634533251752049514769370617 304
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 3763378648720303735603265537179809654669520921977181613635531506492248347498 304
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 95051642687227470286974513518103013974964192852491227128289659422843205174664 304
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 3 test runs
chip_sw_spi_device_pass_through_collision 12801374022056119049304246336151903441499327095196333103836387133574592742298 330
UVM_INFO @ 4250.931848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 20807036885141839780841780926390928625622371209669765746654524044113113623486 330
UVM_INFO @ 4092.508958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 34486218016891966616230655572087110382161341919089885367985787341223699372551 330
UVM_INFO @ 3361.160664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_flash_ctrl_lc_rw_en 114881456670663842897899176153525566444044669051399106774565240354985865129926 312
UVM_INFO @ 3516.642152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 105732083955303367004376631784014230665041201144699337876605985825284376587439 312
UVM_INFO @ 3823.880534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 8853471345525035411805499713973760120774542532118053558493392165918109375805 312
UVM_INFO @ 3480.507361 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 41493957475110907300247028585583529592734432681842054958383454044806979994104 345
UVM_INFO @ 8519.820027 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 49648452059609580921271106873564860485582917615604975036524033827111990802891 345
UVM_INFO @ 8263.810800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 103763982474695395844061144749570555821056415764080322155612646518388855014860 345
UVM_INFO @ 7684.806046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 3 test runs
chip_sw_otp_ctrl_escalation 90527008240904593477044764758621801493381529191327736519373939591481139953007 319
UVM_ERROR @ 3237.547188 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3237.547188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 53784163982106132381845655910598528668344165785739693683765919898223222739338 315
UVM_ERROR @ 3247.130712 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3247.130712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 80010402711398289081720241425835113109304065975326489656746037251538891283815 320
UVM_ERROR @ 3382.999434 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3382.999434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 3 test runs
chip_sw_pwrmgr_full_aon_reset 16833330944131433877534108485904065925998877728594981906276959351247181929627 325
UVM_ERROR @ 6647.999600 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6647.999600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 33670791471555106600391367884769951128439552924020368078006306488788682713087 321
UVM_ERROR @ 5806.892026 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5806.892026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 17125063520258451580798745825093357859348007009829112883500716452405475912711 306
UVM_ERROR @ 2954.564566 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2954.564566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 1658921574098004979273661925675682574306714016771643048815582040620034143918 346
UVM_INFO @ 4609.108094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 103678658246642236793856193110302085114803184007810326367710467525943625480400 346
UVM_INFO @ 4228.229751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 91980823722521048671842513401449165121230793041081996188848849107796521498204 346
UVM_INFO @ 4645.635609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 3 test runs
chip_sw_power_idle_load 101351175897493395929573271309679593053498792171607522014590425967771420111107 321
UVM_INFO @ 15732.713004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 97063404612057417222540461068670553774192376144871990847567228602772124500860 321
UVM_INFO @ 15662.889985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 50442376228124323524558245294330171256784936055708200421907033551515467781904 321
UVM_INFO @ 16175.050450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 3 test runs
chip_sw_power_sleep_load 61773137572133908829413106779871877390890458038894063959404090412766042393271 332
UVM_INFO @ 14377.228442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 75831810387176925908213136484933629744780634332272758859499837147893660095373 340
UVM_INFO @ 15595.211900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 87610836173360034015014672689025292664681998922165734493588507898287524012845 340
UVM_INFO @ 14679.089400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 911713055473417366044728543651869388656164115518252694995107027762356118988 335
UVM_INFO @ 12694.528824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 39430617437146173864939189846308257506553592644769918575112544888890212778909 335
UVM_INFO @ 16161.927735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 106191527940327026736936940897917007709615754149393786745675741031731250074835 335
UVM_INFO @ 15915.830252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 3 test runs
ate_bootstrap_flash_erase 74220066286474136971042665724598482190705725785440595013319396311985415424312 275
UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 32561111176360917563585599501160798473717163062381721099446060337646785583127 275
UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 69506182856265811244497087091781154797729985095716389300422631334688205672510 275
UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 3 test runs
rom_keymgr_functest 36577578551857903332171208760562992741103753377337790609568836022953096020413 330
UVM_ERROR @ 5055.171126 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5055.171126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 24299735032704772082917181323823643734391791697571841593665940471694262809317 330
UVM_ERROR @ 6231.417318 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6231.417318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 103524326136209598175357109471256536016857955758886914878901716963034808521227 330
UVM_ERROR @ 5986.542284 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5986.542284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 2 test runs
chip_sw_rv_dm_access_after_wakeup 94704898146234596453584976411781238588241858106667863402953221605568785506499 332
UVM_INFO @ 13681.984450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 29651230269155786369379240219860157235221378676102578303786947466898975653980 332
UVM_INFO @ 14105.260425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 2 test runs
chip_rv_dm_lc_disabled 102315948641119738304297706475360655624946862179835933172003152008239264406300 268
UVM_INFO @ 11239.207395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 69624056745922034487196229501827351582548312101465477588546442168236150182777 239
UVM_INFO @ 5441.028402 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 2 test runs
rom_e2e_keymgr_init_rom_ext_meas 106781565002249643768598938228348435396843448139478410517773072969711792103844 322
UVM_INFO @ 20794.002082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_keymgr_init_rom_ext_meas 115608582877265496865447409343580208416400236173112713096810137932951374081458 322
UVM_INFO @ 18175.854088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 76113272991882650265206375495882969618538109473553721323055562002057726241357 285
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 47873233743038993015294284791779418268141590047508392507660127675211262463723 310
UVM_INFO @ 3757.943536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' 1 test run
rom_e2e_boot_policy_valid_a_good_b_good_dev 70937668974811591834744497677375151923621210247399030633517808784296228426646 336
UVM_ERROR @ 2852.034672 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 2852.034672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_dev 27710311651269289316762472063888197235897027114366584355238967208981819068637 321
UVM_INFO @ 3970.283933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 93288665280787754443609933017057340147349303329845749478467830090535456522771 322
UVM_INFO @ 17975.559384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:501)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 115302155605996039545367134117127380647084913421263119509628557021571952571675 310
UVM_INFO @ 3106.268008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 71659563052105599073172660888784156943528999621469066581180048764514969945838 319
UVM_INFO @ 5928.493074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 78744591846019289497674976106587446450918718974172887383080388520288471300560 332
UVM_INFO @ 3557.257123 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_prod 52812875554717550113301733849502725633724729438651369222921843642188333957895 311
UVM_INFO @ 26923.866664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:945) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration. 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 90029721369414105572781176059451941809150421284321043194468484322656255555225 312
UVM_INFO @ 3585.885557 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:306)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 19861722532574509747429476164983484265210925396106552252430829365261131600456 310
UVM_INFO @ 3336.990450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * straight after write. 1 test run
chip_sw_rv_dm_access_after_wakeup 52284116532715121451172432701137654443258443242617629075247807773421193804341 312
UVM_INFO @ 3048.366173 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 100247046959186397267157460737265959438110575196956705006949419609248019803923 322
UVM_INFO @ 18356.117590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement 1 test run
rom_raw_unlock 73662271826269712635490925477617398467364582872452200097477502694052693473063 325
UVM_INFO @ 16121.172695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. 1 test run
chip_sw_all_escalation_resets 62290423763399501184130626244556720364145183214677298857263339125687664469431 319
UVM_INFO @ 3349.385294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---