Simulation Results: clkmgr

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.87 %
  • code
  • 98.55 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.07 %
  • branch
  • 98.74 %
  • cond
  • 95.73 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
76.55%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.730s 145.133us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.020s 26.383us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.200s 44.963us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.800s 288.085us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.460s 39.013us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.340s 228.864us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.200s 44.963us 5 5 100.00
clkmgr_csr_aliasing 1.460s 39.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.180s 52.457us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.960s 195.891us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.830s 188.550us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.410s 155.645us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.730s 145.133us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 14.390s 1638.525us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 22.090s 2419.377us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 14.390s 1638.525us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 49.480s 9889.838us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.920s 276.421us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 8.510s 1430.810us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 8.510s 1430.810us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.020s 26.383us 1 1 100.00
clkmgr_csr_rw 1.200s 44.963us 5 5 100.00
clkmgr_csr_aliasing 1.460s 39.013us 1 1 100.00
clkmgr_same_csr_outstanding 2.010s 107.208us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.020s 26.383us 1 1 100.00
clkmgr_csr_rw 1.200s 44.963us 5 5 100.00
clkmgr_csr_aliasing 1.460s 39.013us 1 1 100.00
clkmgr_same_csr_outstanding 2.010s 107.208us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 14 30 46.67
clkmgr_sec_cm 44.430s 10040.836us 0 5 0.00
clkmgr_tl_intg_err 65.210s 10039.764us 14 25 56.00
shadow_reg_update_error 9 20 45.00
clkmgr_shadow_reg_errors 971.990s 200000.000us 9 20 45.00
shadow_reg_read_clear_staged_value 9 20 45.00
clkmgr_shadow_reg_errors 971.990s 200000.000us 9 20 45.00
shadow_reg_storage_error 9 20 45.00
clkmgr_shadow_reg_errors 971.990s 200000.000us 9 20 45.00
shadowed_reset_glitch 9 20 45.00
clkmgr_shadow_reg_errors 971.990s 200000.000us 9 20 45.00
shadow_reg_update_error_with_csr_rw 13 20 65.00
clkmgr_shadow_reg_errors_with_csr_rw 524.280s 200000.000us 13 20 65.00
sec_cm_bus_integrity 14 25 56.00
clkmgr_tl_intg_err 65.210s 10039.764us 14 25 56.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 14.390s 1638.525us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 22.090s 2419.377us 10 10 100.00
sec_cm_meas_config_shadow 9 20 45.00
clkmgr_shadow_reg_errors 971.990s 200000.000us 9 20 45.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.680s 125.553us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.740s 197.022us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.550s 129.385us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_clk_handshake_intersig_mubi 2.010s 252.867us 10 10 100.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.640s 133.106us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.200s 44.963us 5 5 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 44.430s 10040.836us 0 5 0.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.200s 44.963us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.200s 44.963us 5 5 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 44.430s 10040.836us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 5.680s 1299.147us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 109.280s 17554.222us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 14 test runs
clkmgr_shadow_reg_errors 45699597030574472519840575316555625329336515820103760445083520924840299527071 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 15757807392178151408562820044426240542791239689112076398514116192301738659468 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 24701333762798722524174185881794000111920099342792177785651783684709565457757 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 98668724822379879807380368237969642391507029914354514169959473129846505716298 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 4366272429649384128895007813061616798988108576122068097251310382928196902858 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 55416924624637243992289830985927120374714818967895104647906039955195363268501 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 38387652349252646177727581889399831342155846197901818536737673213934504056134 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 75563115687622789926268771518579933184615950567106249587367324512149740707341 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 95469756249624340976581413850356368947885061586728123250050016850810494066138 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 12210202385850774110994980269639969762663659374450193954333909375613158724673 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 55135880828001602677708689089340860825921691386975294285383960114094231720930 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 16507943326473795551059244816312886761650921703061658046925618626764058179606 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 36554488154881089513360862369934408113842566914867412373193087227875105404931 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 107854216266124034771330137885576092161516547861459871868590133284418684946677 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 14 test runs
clkmgr_sec_cm 67486437579344143487475814613618555125785554191897027344889367933151197331340 93
UVM_INFO @ 10040835874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 93582384147154853333821111164323289387000903948907614935055872786214594416909 80
UVM_INFO @ 10005878422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 63322923722125281015255521718188112702830402332163512127347610533672535617437 107
UVM_INFO @ 10069516086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 55930562178499627830484307624756063357746359197173726147492069717946726957734 138
UVM_INFO @ 10139144322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 36934018179412937346420879698683455423861186006421949602201127483875912465527 188
UVM_INFO @ 10105910446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 112606748791534792231669957699214244245865570542867424919413041885508628225251 202
UVM_INFO @ 10113189226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 86020864706531295812406831598322069580811057741548559539251638538279682838680 134
UVM_INFO @ 10042893016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 31607910863570764780500391289531605287730433340617645521576065512618502839289 150
UVM_INFO @ 10152910599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 44811559640249633623134859101719107786890287325193934924731606174644513187730 116
UVM_INFO @ 10160094107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 85323119582810746685366148863506262668892140653363376522508941068709352764187 108
UVM_INFO @ 10020540990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 79741990082242068860037873982497973909499461095438495965735872478494432658903 144
UVM_INFO @ 10039764407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 40928185392156906070320992736877899518643086862809302066766081761819544307828 86
UVM_INFO @ 10006425835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 52239541876056106254403140026635144122676279968734514928320256498619439461096 102
UVM_INFO @ 10032504493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 86507258785660960275841693976989136115712154186823480596107574655726207674362 151
UVM_INFO @ 10053955347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 2 test runs
clkmgr_sec_cm 9542414974507282309258127355557135635897402869805163147758261204478192605588 85
UVM_INFO @ 19030014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 94710877923353213725453134756576430719668189186320085362513193787974721400444 84
UVM_INFO @ 8733880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*) 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 62944356161111568455599971379399257548706902460095627391809952958087905001059 75
UVM_INFO @ 2098313572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 40474792750271631835683861182252010790840433827726208760819825339368046648154 76
UVM_INFO @ 2412071882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 53337802573320789577272353149337267393285503324620148829711661416247016357259 75
UVM_INFO @ 2050726137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 8183358451932063735314012034328871882235629576380407710835072059511675603183 75
UVM_INFO @ 2045950430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---