Simulation Results: csrng

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.27 %
  • code
  • 96.20 %
  • assert
  • 96.94 %
  • func
  • 89.68 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.09%
V2S
99.22%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 16.000s 20.925us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 34.000s 23.539us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 34.000s 15.001us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 46.000s 326.880us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 37.000s 156.668us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 35.000s 73.949us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 34.000s 15.001us 5 5 100.00
csrng_csr_aliasing 37.000s 156.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
alerts 500 500 100.00
csrng_alert 44.000s 3351.559us 500 500 100.00
err 500 500 100.00
csrng_err 32.000s 39.582us 500 500 100.00
cmds 0 25 0.00
csrng_cmds 3600.000s 0.000us 0 25 0.00
life cycle 0 25 0.00
csrng_cmds 3600.000s 0.000us 0 25 0.00
stress_all 25 25 100.00
csrng_stress_all 813.000s 37369.611us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 29.000s 42.786us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 34.000s 56.197us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 15.000s 68.976us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 15.000s 68.976us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 34.000s 23.539us 1 1 100.00
csrng_csr_rw 34.000s 15.001us 5 5 100.00
csrng_csr_aliasing 37.000s 156.668us 1 1 100.00
csrng_same_csr_outstanding 25.000s 181.541us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 34.000s 23.539us 1 1 100.00
csrng_csr_rw 34.000s 15.001us 5 5 100.00
csrng_csr_aliasing 37.000s 156.668us 1 1 100.00
csrng_same_csr_outstanding 25.000s 181.541us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
csrng_tl_intg_err 28.000s 1882.724us 25 25 100.00
sec_cm_config_regwen 20 30 66.67
csrng_regwen 24.000s 36.424us 15 25 60.00
csrng_csr_rw 34.000s 15.001us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 44.000s 3351.559us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 813.000s 37369.611us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 44.000s 3351.559us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 813.000s 37369.611us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 44.000s 3351.559us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 28.000s 1882.724us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
csrng_sec_cm 23.000s 86.935us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 32.000s 95.886us 200 200 100.00
csrng_err 32.000s 39.582us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3600.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 23 test runs
csrng_cmds 32922999604041351780007534584209852228133752808485186277994202596807333869550 100
UVM_INFO @ 37048195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 107089449621887603101018155387214542489659140170977984626190097217079258267734 100
UVM_INFO @ 139927518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 5540003980268607181074739089618826708606171501660897357764104747981422128868 100
UVM_INFO @ 12046205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 18904938222746589562681432928847914650510255621223511539986911726217630190238 100
UVM_INFO @ 32859151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 88796792112667768925404646885083922745447195015778690493388415847479892770423 100
UVM_INFO @ 188867516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98988962618500021439319402911497190274743217689990077635025026213300435526974 100
UVM_INFO @ 55243970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65898297741605117808415173195194498964575195415063269367429511146992081638375 100
UVM_INFO @ 33070215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 41542500050529216289353236953150632466633314876283794780199095985717495490632 100
UVM_INFO @ 150300737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 80358001303970557174295851191248112523043026310992176997316403035914492056403 100
UVM_INFO @ 159999041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 89229160412266420238716264252867948714773986739470779336793245904250766883993 100
UVM_INFO @ 344293814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 78752980520898052254184530799247722669140481076192317039171045156580384126422 100
UVM_INFO @ 118130763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 25662285535863631874665089484748474789789187785912207454292559723705155564767 100
UVM_INFO @ 172933217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 5719068819242618470204742024840980222254463046768710233890636415425544603603 100
UVM_INFO @ 29148602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 36055993124538792358312090913745373111272673025230047397086346244249419796519 100
UVM_INFO @ 53959769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 8088298327615930553662674972285178031464606408355371388784653402324676552383 100
UVM_INFO @ 63704903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 114265002367399764830145043295177026647966850181573203882121205341806832385457 100
UVM_INFO @ 303559548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 73614363143908593064220445258639178521936251884139569353511768532779778014685 100
UVM_INFO @ 41179445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 70754109490171032406219722437940266408369461100039287768567399252607426475475 100
UVM_INFO @ 227708378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 97890951910678035116093048707498274075057291062443845119406167249092273919557 100
UVM_INFO @ 27067910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56602743085075727578542289654724841144621654546084133932498262704741236548739 100
UVM_INFO @ 508381306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 51346749160676017941815864432057037428798818370936815412270844266822858666923 100
UVM_INFO @ 82635167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65250780466339514580529534998965790946481260707168367244140725668542863936037 100
UVM_INFO @ 385253129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 93453130980781922737639021343304916426560769556581464171882300136401690512835 100
UVM_INFO @ 112705735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 8 test runs
csrng_regwen 41726626983382829906702998160891133616926503630031669834378960902951004375125 99
UVM_INFO @ 3107745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 98191499756150652296587313945959847890720668743328180597287492172493061463626 99
UVM_INFO @ 2834343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 71959115655406773101143427950989013550317227471536830583929935520037757417939 99
UVM_INFO @ 5472815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 109714333488427474660107973319239014794791310416671496123150319015669089054375 99
UVM_INFO @ 4337167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 71375904438155531136277311618760699812390721911672424802437821703163586177150 99
UVM_INFO @ 5374143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 43257844192066342654098081769286846917849324790939151175003857375687931263834 99
UVM_INFO @ 3026803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 4414685440412448201176139305755363892310302400778720841153055841176276005549 99
UVM_INFO @ 4715203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 95139162711697981766775883234947923666841598801345761084067137456067938305962 99
UVM_INFO @ 4128176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 4 test runs
csrng_stress_all_with_rand_reset 104251858602273578706763917000262020420376109670808792846903363483109073076677 105
UVM_INFO @ 17780525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 102218326607854335687714970423421773422225820054991206328693905624285445368710 110
UVM_INFO @ 8844695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 62577835486546746345048087192262149788577115688255496256683570365222878023206 107
UVM_INFO @ 74982554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 61245171067056415977732597910228652005391970248969490714541385921317410437524 110
UVM_INFO @ 8467647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 4 test runs
csrng_stress_all_with_rand_reset 104248488484846769444735255078842106571344435749425106285919717431175825621903 None
csrng_cmds 82294602761424775181113766819445697592421448392818145385143793821414464023690 None
csrng_stress_all_with_rand_reset 14031905003380498490457042147233748116844717977558664067809866220965246070189 None
csrng_stress_all_with_rand_reset 114338963757317149652743191549087771368659958779667224110562695238237594277422 None
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 3 test runs
csrng_stress_all_with_rand_reset 83436062886119590845892635113490048878249098115893695356383641743684658537945 214
UVM_INFO @ 17257138762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 78978942334083993401535859118117415136873569346894347887929550729766770460963 148
UVM_INFO @ 2830032985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 42309338850720066437162825089829720648018087921536304618837629039450307949872 107
UVM_INFO @ 35540187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 2 test runs
csrng_regwen 6387391968802491526978531657427145501736869671004751087576851826626678086 99
UVM_INFO @ 3129375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 46398135281791414954891309380511015013849515453651406381425916817387336525851 99
UVM_INFO @ 3067440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 1 test run
csrng_cmds 66650081317975902642682258961704071674397290391311771902931421027195057971495 103
UVM_INFO @ 51869981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---