Simulation Results: edn/edn0

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 95.77 %
  • assert
  • 98.48 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.85 %
  • toggle
  • 97.12 %
  • FSM
  • 92.47 %
Validation stages
V1
100.00%
V2
98.68%
V2S
99.57%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.150s 16.903us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.080s 25.517us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.030s 29.140us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.630s 1128.315us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.590s 402.638us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.530s 34.296us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.030s 29.140us 5 5 100.00
edn_csr_aliasing 1.590s 402.638us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 3.600s 345.430us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 3.600s 345.430us 100 100 100.00
genbits 100 100 100.00
edn_genbits 3.600s 345.430us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.320s 24.958us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.820s 258.577us 200 200 100.00
errs 100 100 100.00
edn_err 1.600s 20.347us 100 100 100.00
disable 92 100 92.00
edn_disable 1.310s 15.004us 50 50 100.00
edn_disable_auto_req_mode 7.490s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 8.410s 406.363us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.100s 17.241us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.140s 26.791us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.550s 135.207us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.550s 135.207us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.080s 25.517us 1 1 100.00
edn_csr_rw 1.030s 29.140us 5 5 100.00
edn_csr_aliasing 1.590s 402.638us 1 1 100.00
edn_same_csr_outstanding 1.250s 23.859us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.080s 25.517us 1 1 100.00
edn_csr_rw 1.030s 29.140us 5 5 100.00
edn_csr_aliasing 1.590s 402.638us 1 1 100.00
edn_same_csr_outstanding 1.250s 23.859us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
edn_sec_cm 53.970s 10424.408us 4 5 80.00
edn_tl_intg_err 3.010s 153.607us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.160s 93.664us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.820s 258.577us 200 200 100.00
sec_cm_main_sm_fsm_sparse 4 5 80.00
edn_sec_cm 53.970s 10424.408us 4 5 80.00
sec_cm_ack_sm_fsm_sparse 4 5 80.00
edn_sec_cm 53.970s 10424.408us 4 5 80.00
sec_cm_fifo_ctr_redun 4 5 80.00
edn_sec_cm 53.970s 10424.408us 4 5 80.00
sec_cm_ctr_redun 4 5 80.00
edn_sec_cm 53.970s 10424.408us 4 5 80.00
sec_cm_main_sm_ctr_local_esc 204 205 99.51
edn_alert 1.820s 258.577us 200 200 100.00
edn_sec_cm 53.970s 10424.408us 4 5 80.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.820s 258.577us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.010s 153.607us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 79.490s 8030.568us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 96979531763492444553669414409155124171408321719002656034771801941550005710329 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 39679947580581788883561822900508252002169477273462689211633120486772652554988 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 43673630348640692717550432790648318217798241534349248232598609199524884130049 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 87124099195559398085989645940418179092955606791393381508691492893354177958739 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66792477064151572208949454243996090077073347479412120403190162478282475679310 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 103383749090536442039189753528574273023838128513486962281494889175934798286796 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 72051133873356528018046343109473638498362152606001641330329556520012918261275 207
UVM_INFO @ 1799168141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 83059938548862357557959663453260010744787236641861112082045358302723057543655 193
UVM_INFO @ 1598638299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 44979591984979529721480626907515781348434796352476147603918018715967121549370 236
UVM_INFO @ 1191061646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 27470234393988867242746900153380287414792120901885935940547623692317899744258 151
UVM_INFO @ 1528564774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 102637719474583722236509895190093736818047638034623507283035128704433937590909 197
UVM_INFO @ 1183194935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 65501450380425931987018553647061490774001099945368078452690517504812472787883 88
UVM_INFO @ 42439199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 54771119948565719617921057167510303668164952407238316135766623758678700108694 88
UVM_INFO @ 29926003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [edn_common_vseq] Timeout waiting for end of ack for alert fatal_alert 1 test run
edn_sec_cm 80852852486687984750094682163564200464873624510514017187543035668417145476293 323
UVM_INFO @ 10424408161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---