Simulation Results: edn/edn1

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.42 %
  • code
  • 96.12 %
  • assert
  • 97.92 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.77 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
98.35%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 0.980s 19.136us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 18.104us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 0.930s 25.822us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.640s 64.220us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.020s 85.817us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.270s 45.722us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 0.930s 25.822us 5 5 100.00
edn_csr_aliasing 1.020s 85.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 2.990s 342.667us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 2.990s 342.667us 100 100 100.00
genbits 100 100 100.00
edn_genbits 2.990s 342.667us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.170s 24.097us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.440s 54.901us 200 200 100.00
errs 100 100 100.00
edn_err 1.250s 19.010us 100 100 100.00
disable 90 100 90.00
edn_disable 1.150s 21.797us 50 50 100.00
edn_disable_auto_req_mode 11.710s 500.000us 40 50 80.00
stress_all 30 30 100.00
edn_stress_all 6.840s 2038.311us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.070s 40.992us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 0.980s 19.333us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.070s 110.701us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.070s 110.701us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.860s 18.104us 1 1 100.00
edn_csr_rw 0.930s 25.822us 5 5 100.00
edn_csr_aliasing 1.020s 85.817us 1 1 100.00
edn_same_csr_outstanding 1.410s 115.612us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.860s 18.104us 1 1 100.00
edn_csr_rw 0.930s 25.822us 5 5 100.00
edn_csr_aliasing 1.020s 85.817us 1 1 100.00
edn_same_csr_outstanding 1.410s 115.612us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.100s 309.130us 5 5 100.00
edn_tl_intg_err 4.200s 369.063us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 0.980s 18.291us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.440s 54.901us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.100s 309.130us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.100s 309.130us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.100s 309.130us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.100s 309.130us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.440s 54.901us 200 200 100.00
edn_sec_cm 4.100s 309.130us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.440s 54.901us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.200s 369.063us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 130.240s 27704.417us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 65671851734786002537793816779289061487689762338725325315161154879977321103472 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 51815063254943820945382277167786878664773986889157465729682557522924834272720 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69329756153418795557259804777018251864990470552497965798484609006229712075261 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 96732842135185986438123285517446456296018603359501996330071644071364273505668 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 9338080093485299044144926275025356199919790319123881873953783348351370023779 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 84142137207444363482216315541194538911894983810498036446099043408341636372394 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 4 test runs
edn_disable_auto_req_mode 101428824592332600344424051781292655865991820395848249234323710712397735342185 88
UVM_INFO @ 233964262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11880349556062645724465702756376401278903775912173999914177183989522266292747 88
UVM_INFO @ 19654987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 67074376721132889823589340268677188454366267184391347168210438042706047735508 88
UVM_INFO @ 57632335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 60113734874399504659954615745876604813980978772660856121019928299703921164554 88
UVM_INFO @ 41407375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 36003645866116414328289983943318960707192285208897993284447566660236537001750 144
UVM_INFO @ 488168608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 37151866987911037038633463060198339397593159485963229130125217370540082405832 172
UVM_INFO @ 1346456863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 106802503362682229628360732401565578411932681172433290954966535907520745035323 275
UVM_INFO @ 2013260473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---