Simulation Results: flash_ctrl

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.97 %
  • code
  • 95.43 %
  • assert
  • 97.02 %
  • func
  • 98.45 %
  • line
  • 96.09 %
  • branch
  • 97.40 %
  • cond
  • 94.73 %
  • toggle
  • 96.41 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
99.47%
V2S
98.53%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 153.150s 1107.021us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 26.790s 32.056us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 22.880s 32.527us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 16.710s 40.072us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 39.330s 9529.734us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 34.030s 824.619us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 18.120s 199.501us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 16.710s 40.072us 5 5 100.00
flash_ctrl_csr_aliasing 34.030s 824.619us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 12.910s 17.947us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 11.100s 26.450us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 21.080s 49.814us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 74.020s 58.909us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1838.870s 1321291.240us 3 3 100.00
flash_ctrl_hw_rma_reset 756.470s 160181.863us 20 20 100.00
flash_ctrl_lcmgr_intg 14.920s 78.692us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 1932.870s 258003.810us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 314.440s 30596.718us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 134.620s 10324.963us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3220.490s 150632.451us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 87.360s 1547.790us 5 5 100.00
rd_buff_eviction_w_ecc 104 105 99.05
flash_ctrl_rw_evict 34.100s 77.913us 40 40 100.00
flash_ctrl_rw_evict_all_en 35.000s 83.791us 39 40 97.50
flash_ctrl_re_evict 33.180s 72.203us 25 25 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 274.790s 1620.564us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 274.790s 1620.564us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 488.190s 11545.768us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 34.660s 698.472us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 694.740s 162.732us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 753.830s 6213.302us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 547.870s 4058.548us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1646.240s 4672.116us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 13.760s 77.796us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 155.140s 7317.413us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 24.770s 23.968us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 18.600s 16.747us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 1609.900s 1128.837us 5 5 100.00
secret_partition 129 130 99.23
flash_ctrl_hw_sec_otp 187.890s 36032.516us 50 50 100.00
flash_ctrl_otp_reset 117.140s 352.980us 79 80 98.75
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1838.870s 1321291.240us 3 3 100.00
interrupts 100 100 100.00
flash_ctrl_intr_rd 196.040s 8050.667us 40 40 100.00
flash_ctrl_intr_wr 87.150s 11400.738us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 328.030s 17266.195us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 291.140s 365685.181us 10 10 100.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 67.410s 17243.739us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 57.010s 683.690us 5 5 100.00
double_bit_err 35 35 100.00
flash_ctrl_read_word_sweep_derr 23.030s 33.767us 5 5 100.00
flash_ctrl_ro_derr 125.740s 865.881us 10 10 100.00
flash_ctrl_rw_derr 210.420s 2423.505us 10 10 100.00
flash_ctrl_derr_detect 130.860s 618.791us 5 5 100.00
flash_ctrl_integrity 454.390s 17449.421us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 19.210s 58.931us 5 5 100.00
flash_ctrl_ro_serr 109.010s 1481.970us 10 10 100.00
flash_ctrl_rw_serr 197.440s 28874.508us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 70.040s 4937.450us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 61.160s 926.788us 5 5 100.00
scramble 59 62 95.16
flash_ctrl_wo 160.350s 11462.353us 20 20 100.00
flash_ctrl_write_word_sweep 14.630s 81.504us 1 1 100.00
flash_ctrl_read_word_sweep 13.460s 57.117us 1 1 100.00
flash_ctrl_ro 106.870s 865.452us 20 20 100.00
flash_ctrl_rw 3604.012s 0.000us 17 20 85.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 28.640s 832.257us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 854.900s 673173.980us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 95.050s 10020.284us 20 20 100.00
alert_test 10 10 100.00
flash_ctrl_alert_test 15.070s 72.830us 10 10 100.00
intr_test 10 10 100.00
flash_ctrl_intr_test 14.240s 20.031us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
flash_ctrl_tl_errors 20.590s 123.435us 25 25 100.00
tl_d_illegal_access 25 25 100.00
flash_ctrl_tl_errors 20.590s 123.435us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 22.880s 32.527us 1 1 100.00
flash_ctrl_csr_rw 16.710s 40.072us 5 5 100.00
flash_ctrl_csr_aliasing 34.030s 824.619us 1 1 100.00
flash_ctrl_same_csr_outstanding 19.410s 407.630us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 22.880s 32.527us 1 1 100.00
flash_ctrl_csr_rw 16.710s 40.072us 5 5 100.00
flash_ctrl_csr_aliasing 34.030s 824.619us 1 1 100.00
flash_ctrl_same_csr_outstanding 19.410s 407.630us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 68.770s 178.197us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 68.770s 178.197us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 68.770s 178.197us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 68.770s 178.197us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 110.300s 427.565us 20 20 100.00
tl_intg_err 30 30 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
flash_ctrl_tl_intg_err 624.330s 3427.423us 25 25 100.00
sec_cm_reg_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 624.330s 3427.423us 25 25 100.00
sec_cm_host_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 624.330s 3427.423us 25 25 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 26.970s 72.344us 3 3 100.00
flash_ctrl_wr_intg 16.240s 293.856us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 153.150s 1107.021us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 259 260 99.62
flash_ctrl_otp_reset 117.140s 352.980us 79 80 98.75
flash_ctrl_disable 24.770s 23.968us 50 50 100.00
flash_ctrl_sec_info_access 95.280s 28956.435us 50 50 100.00
flash_ctrl_connect 18.600s 16.747us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 13.570s 39.572us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.710s 40.072us 5 5 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 68.770s 178.197us 20 20 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.710s 40.072us 5 5 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 68.770s 178.197us 20 20 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.710s 40.072us 5 5 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 68.770s 178.197us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 24.770s 23.968us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 26.970s 72.344us 3 3 100.00
flash_ctrl_access_after_disable 13.160s 76.877us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 17.700s 29.199us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 24.770s 23.968us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 34.660s 698.472us 10 10 100.00
sec_cm_mem_scramble 17 20 85.00
flash_ctrl_rw 3604.012s 0.000us 17 20 85.00
sec_cm_mem_integrity 25 25 100.00
flash_ctrl_rw_serr 197.440s 28874.508us 10 10 100.00
flash_ctrl_rw_derr 210.420s 2423.505us 10 10 100.00
flash_ctrl_integrity 454.390s 17449.421us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1838.870s 1321291.240us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 15.350s 941.389us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 2 5 40.00
flash_ctrl_phy_host_grant_err 13.830s 22.713us 2 5 40.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 14.480s 30.327us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2410.130s 1598.758us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.430s 167.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 444.900s 2479.890us 3 3 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 3 test runs
flash_ctrl_phy_host_grant_err 43917516492567338582872844381142478744081164891494113829220554840691241593165 125
UVM_ERROR @ 10674.8 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 10674.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 19913015521258453174715398342154236171049135341626286992936651624419957400208 125
UVM_ERROR @ 11940.3 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 11940.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 9699917066732705166905938420210035685074846009948353663542671427686428498913 125
UVM_ERROR @ 19581.1 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 19581.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 3 test runs
flash_ctrl_rw 12913592802292240921987257998448028837389832352016765149117366520733971649967 None
flash_ctrl_rw 35711295736176615513243619247679043374250713874114772050921309985837906908538 None
flash_ctrl_rw 36515681772129903300147116577746339699541769520026373590103110985433969275460 None
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 1 test run
flash_ctrl_rw_evict_all_en 44891642993470978935551224463068302617108078641527307040661266501366919840345 108
UVM_INFO @ 63972.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'dst_req_o' 1 test run
flash_ctrl_otp_reset 2861007106973205620965937669793153107691031853316626492203796847668786935187 124
UVM_ERROR @ 2633.9 ns: (prim_sync_reqack.sv:364) [ASSERT FAILED] SyncReqAckAckNeedsReq
UVM_INFO @ 2633.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---