Simulation Results: gpio

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.78 %
  • code
  • 94.91 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 80.52 %
Validation stages
V1
100.00%
V2
94.90%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 1.550s 196.196us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.700s 397.704us 10 10 100.00
gpio_smoke_en_cdc_prim 1.850s 626.276us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.770s 48.202us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 0.970s 16.410us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 0.940s 52.346us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 3.200s 706.355us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 1.280s 369.997us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.160s 183.628us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 0.940s 52.346us 5 5 100.00
gpio_csr_aliasing 1.280s 369.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.680s 519.037us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.430s 230.314us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.180s 56.609us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.810s 115.194us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 3.090s 278.246us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 3.800s 346.879us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 20.160s 968.191us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 3.950s 139.078us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.440s 669.733us 10 10 100.00
stress_all 2 10 20.00
gpio_stress_all 97.440s 21805.807us 2 10 20.00
alert_test 10 10 100.00
gpio_alert_test 0.920s 57.902us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.950s 16.836us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 3.380s 752.304us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 3.380s 752.304us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 0.940s 52.346us 5 5 100.00
gpio_same_csr_outstanding 1.110s 143.390us 5 5 100.00
gpio_csr_aliasing 1.280s 369.997us 1 1 100.00
gpio_csr_hw_reset 0.970s 16.410us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 0.940s 52.346us 5 5 100.00
gpio_same_csr_outstanding 1.110s 143.390us 5 5 100.00
gpio_csr_aliasing 1.280s 369.997us 1 1 100.00
gpio_csr_hw_reset 0.970s 16.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.880s 210.244us 25 25 100.00
gpio_sec_cm 1.440s 117.202us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.880s 210.244us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 8 10 80.00
gpio_rand_straps 0.920s 12.381us 8 10 80.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 9.070s 3188.955us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 10 test runs
gpio_stress_all 2367083979380650737350397882417101393075361799214635070332323555059680724179 1009
UVM_INFO @ 6546999757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 64087827946075839934006209051134825126793947160070389213805205153426192318240 129
UVM_INFO @ 2996232129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 100558332869247931414563847675053326980683603343938425437735548887240715936326 75
UVM_INFO @ 1310714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 93835718190521286673913009172678826545822748949623068349945423443363817138244 332
UVM_INFO @ 3641130871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 109933191234625946860326045922712850098677015468590303519721780081172078970227 2068
UVM_INFO @ 4767482436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 24611731169247607377996178992183222744600440710216985955828604944788287331814 470
UVM_INFO @ 1686732925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 41896490537309079693502765632042223119045090499877192567298550342499148111287 893
UVM_INFO @ 12535813827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 78091117596756956301640565951675032224958438120834071342953133049850691547780 671
UVM_INFO @ 810582794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 76778125455464559867734440010778347014663607782052664258809713440350979041047 127
UVM_INFO @ 1022550451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 106203492741092291691231115609055871318857162890220037177388709284271093177828 75
UVM_INFO @ 1352677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 7 test runs
gpio_stress_all_with_rand_reset 15130218282173179134425966403716873104874613118152768793113706705730402957521 80
UVM_INFO @ 11680430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 70130790459303814592435747098616027409520153293506527147578766164347715120849 80
UVM_INFO @ 119529845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 101117199083707405347626625086552550058610105769099663257267711838330758433659 258
UVM_INFO @ 3188955031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 92002440063220699435193224460707179022914796383721016639339963088962863231323 192
UVM_INFO @ 1190778005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 98978761132518516876672149516044055067719843469260509330529629636508105878284 80
UVM_INFO @ 594523292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24571321715687312716093065195505714500313538168548423527149362150085614871836 82
UVM_INFO @ 1421468918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 55495073265726009214453115230155721424940088649949770942903091163664289122544 80
UVM_INFO @ 14823110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 3 test runs
gpio_stress_all_with_rand_reset 81469239676631984088805603967819558848147763812316830714896896275872919943873 78
UVM_INFO @ 9263982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 82291441540426840280579960618509513942592122663011358216735615938408303248158 78
UVM_INFO @ 2990116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100480282405925987370318900439957639196861770812871820258988232517002762236788 80
UVM_INFO @ 300288891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---