Simulation Results: hmac

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.81 %
  • code
  • 99.22 %
  • assert
  • 97.60 %
  • func
  • 99.62 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.69 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 11.140s 4944.382us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.400s 190.707us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.180s 59.095us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.670s 1379.197us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.540s 158.663us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 488.280s 45654.126us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.180s 59.095us 5 5 100.00
hmac_csr_aliasing 7.540s 158.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 57.230s 1745.665us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 88.860s 2657.676us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 294.580s 41857.275us 30 30 100.00
hmac_test_sha384_vectors 605.200s 112408.482us 75 75 100.00
hmac_test_sha512_vectors 587.940s 278755.787us 75 75 100.00
hmac_test_hmac256_vectors 16.180s 1909.261us 50 50 100.00
hmac_test_hmac384_vectors 21.260s 6706.195us 60 60 100.00
hmac_test_hmac512_vectors 18.820s 984.547us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 40.300s 3796.410us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1302.610s 9513.573us 10 10 100.00
error 10 10 100.00
hmac_error 101.020s 38891.877us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 129.490s 12981.924us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 11.140s 4944.382us 10 10 100.00
hmac_long_msg 57.230s 1745.665us 10 10 100.00
hmac_back_pressure 88.860s 2657.676us 25 25 100.00
hmac_datapath_stress 1302.610s 9513.573us 10 10 100.00
hmac_burst_wr 40.300s 3796.410us 50 50 100.00
hmac_stress_all 2182.080s 283229.232us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 11.140s 4944.382us 10 10 100.00
hmac_long_msg 57.230s 1745.665us 10 10 100.00
hmac_back_pressure 88.860s 2657.676us 25 25 100.00
hmac_datapath_stress 1302.610s 9513.573us 10 10 100.00
hmac_wipe_secret 129.490s 12981.924us 10 10 100.00
hmac_test_sha256_vectors 294.580s 41857.275us 30 30 100.00
hmac_test_sha384_vectors 605.200s 112408.482us 75 75 100.00
hmac_test_sha512_vectors 587.940s 278755.787us 75 75 100.00
hmac_test_hmac256_vectors 16.180s 1909.261us 50 50 100.00
hmac_test_hmac384_vectors 21.260s 6706.195us 60 60 100.00
hmac_test_hmac512_vectors 18.820s 984.547us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 11.140s 4944.382us 10 10 100.00
hmac_long_msg 57.230s 1745.665us 10 10 100.00
hmac_back_pressure 88.860s 2657.676us 25 25 100.00
hmac_datapath_stress 1302.610s 9513.573us 10 10 100.00
hmac_burst_wr 40.300s 3796.410us 50 50 100.00
hmac_error 101.020s 38891.877us 10 10 100.00
hmac_wipe_secret 129.490s 12981.924us 10 10 100.00
hmac_test_sha256_vectors 294.580s 41857.275us 30 30 100.00
hmac_test_sha384_vectors 605.200s 112408.482us 75 75 100.00
hmac_test_sha512_vectors 587.940s 278755.787us 75 75 100.00
hmac_test_hmac256_vectors 16.180s 1909.261us 50 50 100.00
hmac_test_hmac384_vectors 21.260s 6706.195us 60 60 100.00
hmac_test_hmac512_vectors 18.820s 984.547us 75 75 100.00
hmac_stress_all 2182.080s 283229.232us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2182.080s 283229.232us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.940s 30.779us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.990s 21.445us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.260s 919.437us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.260s 919.437us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.400s 190.707us 1 1 100.00
hmac_csr_rw 1.180s 59.095us 5 5 100.00
hmac_csr_aliasing 7.540s 158.663us 1 1 100.00
hmac_same_csr_outstanding 2.130s 416.455us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.400s 190.707us 1 1 100.00
hmac_csr_rw 1.180s 59.095us 5 5 100.00
hmac_csr_aliasing 7.540s 158.663us 1 1 100.00
hmac_same_csr_outstanding 2.130s 416.455us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.350s 178.315us 5 5 100.00
hmac_tl_intg_err 5.030s 1103.713us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.030s 1103.713us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 11.140s 4944.382us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.130s 155.694us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 525.750s 57454.150us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.060s 56.094us 1 1 100.00