Simulation Results: keymgr

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.87 %
  • code
  • 98.84 %
  • assert
  • 97.72 %
  • func
  • 91.05 %
  • line
  • 99.20 %
  • branch
  • 99.18 %
  • cond
  • 98.08 %
  • toggle
  • 97.75 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.13%
V2S
98.15%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 3.440s 398.355us 30 30 100.00
random 30 30 100.00
keymgr_random 5.970s 198.307us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.150s 43.649us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.650s 108.047us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 9.590s 775.859us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 8.010s 909.526us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.980s 37.657us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.650s 108.047us 5 5 100.00
keymgr_csr_aliasing 8.010s 909.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 4.570s 355.907us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 3.960s 633.687us 20 20 100.00
keymgr_sideload_kmac 3.310s 456.838us 20 20 100.00
keymgr_sideload_aes 2.960s 101.234us 20 20 100.00
keymgr_sideload_otbn 3.880s 221.930us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 3.340s 130.659us 30 30 100.00
lc_disable 44 50 88.00
keymgr_lc_disable 4.970s 148.504us 44 50 88.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 5.280s 498.474us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 5.700s 655.289us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 4.620s 137.361us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 3.270s 172.680us 20 20 100.00
stress_all 48 50 96.00
keymgr_stress_all 44.130s 1745.332us 48 50 96.00
intr_test 10 10 100.00
keymgr_intr_test 1.330s 160.056us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.150s 50.324us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 3.980s 717.310us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 3.980s 717.310us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.150s 43.649us 1 1 100.00
keymgr_csr_rw 1.650s 108.047us 5 5 100.00
keymgr_csr_aliasing 8.010s 909.526us 1 1 100.00
keymgr_same_csr_outstanding 3.310s 393.381us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.150s 43.649us 1 1 100.00
keymgr_csr_rw 1.650s 108.047us 5 5 100.00
keymgr_csr_aliasing 8.010s 909.526us 1 1 100.00
keymgr_same_csr_outstanding 3.310s 393.381us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
keymgr_tl_intg_err 7.200s 4060.757us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 3.530s 976.117us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 3.530s 976.117us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 3.530s 976.117us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 3.530s 976.117us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 10.450s 1326.887us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 7.200s 4060.757us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 3.530s 976.117us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 4.570s 355.907us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 5.970s 198.307us 30 30 100.00
keymgr_csr_rw 1.650s 108.047us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 5.970s 198.307us 30 30 100.00
keymgr_csr_rw 1.650s 108.047us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 5.970s 198.307us 30 30 100.00
keymgr_csr_rw 1.650s 108.047us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 44 50 88.00
keymgr_lc_disable 4.970s 148.504us 44 50 88.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 4.620s 137.361us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 4.620s 137.361us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 5.970s 198.307us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 3.510s 127.527us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 6.240s 816.717us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 44 50 88.00
keymgr_lc_disable 4.970s 148.504us 44 50 88.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 6.240s 816.717us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 6.240s 816.717us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 6.240s 816.717us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 1176.749us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 6.240s 816.717us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 12 20 60.00
keymgr_stress_all_with_rand_reset 14.890s 1504.918us 12 20 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
keymgr_stress_all_with_rand_reset 96387884789901601743352869392590613195737152527678234176812256687081047162604 2062
UVM_INFO @ 576412816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 28295637516438230334200060125712765551529873693421947718421925932342993036953 396
UVM_INFO @ 1747937759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 82656247177685555414479220713490399048095787094591915231496810289081349753883 1347
UVM_INFO @ 1974950343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95677797559479335485321485281331198171188887411066645506864257091190028593597 757
UVM_INFO @ 1419432801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 59597801362824255580202052671310695159917648226766953772458285152805269852679 1542
UVM_INFO @ 1093803568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46134544246996672457712169308516420165503814729115105920878883198986882763398 526
UVM_INFO @ 562242564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 37681087837582650689615502492074195789153087541407118708594307511866911431978 1299
UVM_INFO @ 1383159598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:778) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 3 test runs
keymgr_lc_disable 103219733117961168840658071757934833993595110944930511472424831626258432841605 340
UVM_INFO @ 181149357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 91096165796611461789370920117494272078699635274885520885355401826081178808223 216
UVM_INFO @ 319853072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 57647355983431954849673543887797032896176622246284568118743511765204136746166 337
UVM_INFO @ 107760507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:778) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 2 test runs
keymgr_lc_disable 45819150534488639911780318485611098910811502118220499635751369851930634043530 181
UVM_INFO @ 69720227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 34760159978884403449059393085379037619873406667426658046917867254603048219575 131
UVM_INFO @ 15811250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 2 test runs
keymgr_stress_all 49066465044015176610218754714710022052613636510868322739636420207429283888725 85
UVM_INFO @ 7285414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 76839048557816594998893992517210952560035279810502044582124808826374116772986 85
UVM_INFO @ 64646813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:663) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) 1 test run
keymgr_stress_all_with_rand_reset 109576576944719459991145201448599870316949586219259984112954763171433040876662 910
UVM_INFO @ 886932347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:547) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Sealing Aes 1 test run
keymgr_lc_disable 8226998893904982147097247339119178557011550374196914586974924285421845274958 278
UVM_INFO @ 56064236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---