Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.33 %
  • code
  • 85.73 %
  • assert
  • 94.83 %
  • func
  • 96.42 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 81.91 %
  • toggle
  • 88.33 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
98.83%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.660s 568.412us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.210s 58.510us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.290s 19.111us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.470s 258.425us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.820s 159.520us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.890s 26.113us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.290s 19.111us 5 5 100.00
lc_ctrl_csr_aliasing 1.820s 159.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.520s 376.401us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.350s 445.680us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.190s 13.874us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.200s 214.509us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_errors 17 20 85.00
lc_ctrl_errors 8.020s 709.755us 17 20 85.00
security_escalation 136 140 97.14
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_prog_failure 3.200s 214.509us 20 20 100.00
lc_ctrl_errors 8.020s 709.755us 17 20 85.00
lc_ctrl_security_escalation 8.710s 1096.342us 20 20 100.00
lc_ctrl_jtag_state_failure 43.220s 12272.794us 20 20 100.00
lc_ctrl_jtag_prog_failure 8.160s 843.647us 20 20 100.00
lc_ctrl_jtag_errors 34.230s 2544.391us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 10.620s 1480.546us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.040s 5657.516us 20 20 100.00
lc_ctrl_jtag_prog_failure 8.160s 843.647us 20 20 100.00
lc_ctrl_jtag_errors 34.230s 2544.391us 19 20 95.00
lc_ctrl_jtag_access 8.630s 976.490us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 15.490s 14147.546us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.070s 210.737us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.750s 734.595us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.190s 2494.235us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.060s 1971.032us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.550s 87.523us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.450s 554.368us 10 10 100.00
lc_ctrl_jtag_alert_test 1.960s 288.973us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 5.280s 731.896us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.260s 15.533us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 166.470s 24096.383us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.470s 47.879us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.450s 459.768us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.450s 459.768us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.210s 58.510us 1 1 100.00
lc_ctrl_csr_rw 1.290s 19.111us 5 5 100.00
lc_ctrl_csr_aliasing 1.820s 159.520us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.900s 251.511us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.210s 58.510us 1 1 100.00
lc_ctrl_csr_rw 1.290s 19.111us 5 5 100.00
lc_ctrl_csr_aliasing 1.820s 159.520us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.900s 251.511us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
lc_ctrl_tl_intg_err 3.290s 681.631us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.290s 681.631us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.350s 445.680us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 11.440s 234.457us 20 20 100.00
lc_ctrl_sec_cm 10.560s 980.759us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 8.710s 1096.342us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.520s 376.401us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.040s 5657.516us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.860s 621.889us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.860s 621.889us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 7.990s 499.640us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.260s 1586.959us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.260s 1586.959us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
lc_ctrl_stress_all_with_rand_reset 82.290s 38363.154us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 7 test runs
lc_ctrl_stress_all_with_rand_reset 44362260044389941397090321940027183651564442012243719124199675714251017805855 5415
UVM_INFO @ 861184276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54476428743381274522282031988806280192103173981274198460455381130272594652674 1753
UVM_INFO @ 570785002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 63259644131786258895062585665954998191532575006598071992425041464908465857836 4476
UVM_INFO @ 17265864360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 24132282220901619668088753058195637808462164660386862110778058475371681500327 2880
UVM_INFO @ 446118398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 42621802035953373007871902093318879251927581312054284400509025040367093623467 2429
UVM_INFO @ 271520354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 27750263335924256872178260915387042350411186699365590975466837188192179934850 1392
UVM_INFO @ 2408455170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 55242712858340071969523883282059337537450440422357413030808359541583528797092 1356
UVM_INFO @ 6769473104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [lc_ctrl_common_vseq] wait timeout occurred! 1 test run
lc_ctrl_stress_all_with_rand_reset 40317415233028063360078108709652565729837538510437397485249114811470508524113 354
UVM_INFO @ 11856289678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---