Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.35 %
  • code
  • 85.88 %
  • assert
  • 95.11 %
  • func
  • 96.06 %
  • line
  • 97.26 %
  • branch
  • 93.95 %
  • cond
  • 81.62 %
  • toggle
  • 88.33 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.06%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.080s 364.525us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.180s 89.345us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.150s 146.834us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.240s 101.867us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 244.272us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.540s 158.431us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.150s 146.834us 5 5 100.00
lc_ctrl_csr_aliasing 1.290s 244.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 7.040s 66.159us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.950s 2873.505us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.150s 14.084us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.040s 183.305us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 8.290s 1680.288us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_prog_failure 3.040s 183.305us 20 20 100.00
lc_ctrl_errors 8.290s 1680.288us 19 20 95.00
lc_ctrl_security_escalation 7.890s 2075.728us 20 20 100.00
lc_ctrl_jtag_state_failure 44.000s 4458.309us 20 20 100.00
lc_ctrl_jtag_prog_failure 7.790s 520.750us 20 20 100.00
lc_ctrl_jtag_errors 36.970s 3201.506us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 7.340s 3718.631us 20 20 100.00
lc_ctrl_jtag_state_post_trans 16.510s 761.546us 20 20 100.00
lc_ctrl_jtag_prog_failure 7.790s 520.750us 20 20 100.00
lc_ctrl_jtag_errors 36.970s 3201.506us 19 20 95.00
lc_ctrl_jtag_access 10.040s 1382.671us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 15.430s 2485.849us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.200s 366.102us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.740s 153.045us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 12.880s 1992.280us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 7.570s 2086.145us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.820s 48.139us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.530s 1234.964us 10 10 100.00
lc_ctrl_jtag_alert_test 2.110s 372.933us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 7.250s 3342.875us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.260s 12.488us 10 10 100.00
stress_all 8 10 80.00
lc_ctrl_stress_all 220.450s 18574.255us 8 10 80.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.320s 31.670us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.010s 131.880us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.010s 131.880us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.180s 89.345us 1 1 100.00
lc_ctrl_csr_rw 1.150s 146.834us 5 5 100.00
lc_ctrl_csr_aliasing 1.290s 244.272us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.500s 47.382us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.180s 89.345us 1 1 100.00
lc_ctrl_csr_rw 1.150s 146.834us 5 5 100.00
lc_ctrl_csr_aliasing 1.290s 244.272us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.500s 47.382us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
lc_ctrl_tl_intg_err 2.940s 864.010us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 2.940s 864.010us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.950s 2873.505us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.280s 936.618us 20 20 100.00
lc_ctrl_sec_cm 7.860s 466.919us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.890s 2075.728us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 7.040s 66.159us 20 20 100.00
lc_ctrl_jtag_state_post_trans 16.510s 761.546us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 6.740s 321.383us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 6.740s 321.383us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 13.560s 5780.755us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.620s 1696.122us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.620s 1696.122us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 54.470s 4276.975us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 1564885239874644817047609190053457955788964341311227031519900982260864660605 200
UVM_INFO @ 793614851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108123412078742231429705897109838841037063696806768882458153042696200603108957 840
UVM_INFO @ 8698034034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 106599043263959395051462630918813923413235734380553788706688870605757550330372 4532
UVM_INFO @ 1859872864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29665067673329928000503171051159899311461118732765477944216255692814478468199 2434
UVM_INFO @ 2617808617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_stress_all 37955477955084468472155380890034310070607482760525243298936559870021817876082 3774
UVM_INFO @ 20104287249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 109211685606619184727061541691230234859930920216148813758607989435364904912636 313
UVM_INFO @ 358841794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 33123026039770268630428445922049221112963406828934479136997311817259820420304 1152
UVM_INFO @ 161924154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all 28238770749115661237130683750951422894868740451755047466565790791150357613014 12131
UVM_INFO @ 29774224752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:247) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* 1 test run
lc_ctrl_stress_all_with_rand_reset 28774382706478721360493462869682406336075683445605383688081987273660790501756 1463
UVM_INFO @ 774069580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---